80486DX2-66/86Box-fork
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Applied mainline PCem commit: Added code generation for RMW versions of SHL/SHR/SAR.

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This commit is contained in:
OBattler
2016-11-17 21:36:09 +01:00
parent 413fba4b16
commit 79d5fb108f
3 changed files with 41 additions and 27 deletions
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65
src/codegen_ops_shift.h
View File

@@ -1,6 +1,20 @@
#define SHIFT(size, size2, count, res_store) \ #define SHIFT(size, size2, res_store, immediate) \
if ((fetchdat & 0xc0) == 0xc0) \
{ \
reg = LOAD_REG_ ## size(fetchdat & 7); \
if (immediate) count = (fetchdat >> 8) & 0x1f; \
} \
else \
{ \
target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32); \
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc); \
SAVE_EA(); \
MEM_CHECK_WRITE_ ## size(target_seg); \
reg = MEM_LOAD_ADDR_EA_ ## size ## _NO_ABRT(target_seg); \
if (immediate) count = fastreadb(cs + op_pc + 1) & 0x1f; \
} \
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op2, count); \ STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op2, count); \
reg = LOAD_REG_ ## size(fetchdat & 7); \ \
res_store((uint32_t)&cpu_state.flags_op1, reg); \ res_store((uint32_t)&cpu_state.flags_op1, reg); \
\ \
switch (fetchdat & 0x38) \ switch (fetchdat & 0x38) \
@@ -22,93 +36,90 @@
} \ } \
\ \
res_store((uint32_t)&cpu_state.flags_res, reg); \ res_store((uint32_t)&cpu_state.flags_res, reg); \
STORE_REG_ ## size ## _RELEASE(reg); if ((fetchdat & 0xc0) == 0xc0) \
STORE_REG_ ## size ## _RELEASE(reg); \
else \
{ \
LOAD_EA(); \
MEM_STORE_ADDR_EA_ ## size ## _NO_ABRT(target_seg, reg); \
}
static uint32_t ropC0(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block) static uint32_t ropC0(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{ {
x86seg *target_seg;
int count; int count;
int reg; int reg;
if ((fetchdat & 0xc0) != 0xc0)
return 0;
if ((fetchdat & 0x38) < 0x20) if ((fetchdat & 0x38) < 0x20)
return 0; return 0;
count = (fetchdat >> 8) & 0x1f; SHIFT(B, 8, STORE_HOST_REG_ADDR_BL, 1);
SHIFT(B, 8, count, STORE_HOST_REG_ADDR_BL);
return op_pc + 2; return op_pc + 2;
} }
static uint32_t ropC1_w(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block) static uint32_t ropC1_w(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{ {
x86seg *target_seg;
int count; int count;
int reg; int reg;
if ((fetchdat & 0xc0) != 0xc0)
return 0;
if ((fetchdat & 0x38) < 0x20) if ((fetchdat & 0x38) < 0x20)
return 0; return 0;
count = (fetchdat >> 8) & 0x1f; SHIFT(W, 16, STORE_HOST_REG_ADDR_WL, 1);
SHIFT(W, 16, count, STORE_HOST_REG_ADDR_WL);
return op_pc + 2; return op_pc + 2;
} }
static uint32_t ropC1_l(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block) static uint32_t ropC1_l(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{ {
x86seg *target_seg;
int count; int count;
int reg; int reg;
if ((fetchdat & 0xc0) != 0xc0)
return 0;
if ((fetchdat & 0x38) < 0x20) if ((fetchdat & 0x38) < 0x20)
return 0; return 0;
count = (fetchdat >> 8) & 0x1f; SHIFT(L, 32, STORE_HOST_REG_ADDR, 1);
SHIFT(L, 32, count, STORE_HOST_REG_ADDR);
return op_pc + 2; return op_pc + 2;
} }
static uint32_t ropD0(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block) static uint32_t ropD0(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{ {
x86seg *target_seg;
int count = 1;
int reg; int reg;
if ((fetchdat & 0xc0) != 0xc0)
return 0;
if ((fetchdat & 0x38) < 0x20) if ((fetchdat & 0x38) < 0x20)
return 0; return 0;
SHIFT(B, 8, 1, STORE_HOST_REG_ADDR_BL); SHIFT(B, 8, STORE_HOST_REG_ADDR_BL, 0);
return op_pc + 1; return op_pc + 1;
} }
static uint32_t ropD1_w(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block) static uint32_t ropD1_w(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{ {
x86seg *target_seg;
int count = 1;
int reg; int reg;
if ((fetchdat & 0xc0) != 0xc0)
return 0;
if ((fetchdat & 0x38) < 0x20) if ((fetchdat & 0x38) < 0x20)
return 0; return 0;
SHIFT(W, 16, 1, STORE_HOST_REG_ADDR_WL); SHIFT(W, 16, STORE_HOST_REG_ADDR_WL, 0);
return op_pc + 1; return op_pc + 1;
} }
static uint32_t ropD1_l(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block) static uint32_t ropD1_l(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{ {
x86seg *target_seg;
int count = 1;
int reg; int reg;
if ((fetchdat & 0xc0) != 0xc0)
return 0;
if ((fetchdat & 0x38) < 0x20) if ((fetchdat & 0x38) < 0x20)
return 0; return 0;
SHIFT(L, 32, 1, STORE_HOST_REG_ADDR); SHIFT(L, 32, STORE_HOST_REG_ADDR, 0);
return op_pc + 1; return op_pc + 1;
} }

2
src/codegen_ops_x86-64.h
View File

@@ -5147,6 +5147,8 @@ static void LOAD_EA()
addbyte(0x24); addbyte(0x24);
} }
#define MEM_CHECK_WRITE_B MEM_CHECK_WRITE
static void MEM_CHECK_WRITE(x86seg *seg) static void MEM_CHECK_WRITE(x86seg *seg)
{ {
uint8_t *jump1, *jump2; uint8_t *jump1, *jump2;

1
src/codegen_ops_x86.h
View File

@@ -3633,6 +3633,7 @@ static void LOAD_EA()
addbyte(12); addbyte(12);
} }
#define MEM_CHECK_WRITE_B MEM_CHECK_WRITE
static void MEM_CHECK_WRITE(x86seg *seg) static void MEM_CHECK_WRITE(x86seg *seg)
{ {
CHECK_SEG_WRITE(seg); CHECK_SEG_WRITE(seg);