2014-04-09 04:45:46 +05:30
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// Copyright 2014 Citra Emulator Project
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// Licensed under GPLv2
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// Refer to the license.txt file included.
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2014-04-05 10:53:51 +05:30
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2014-04-09 05:45:08 +05:30
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#include "common/common_types.h"
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#include "common/log.h"
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#include "core/core.h"
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2014-04-27 22:09:57 +05:30
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#include "core/mem_map.h"
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2014-05-18 01:37:06 +05:30
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#include "core/hle/kernel/thread.h"
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2014-05-18 02:20:33 +05:30
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#include "core/hw/gpu.h"
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2014-04-09 05:45:08 +05:30
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#include "video_core/video_core.h"
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2014-04-05 10:53:51 +05:30
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2014-05-23 05:31:04 +05:30
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2014-05-18 02:20:33 +05:30
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namespace GPU {
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2014-04-05 10:53:51 +05:30
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2014-04-27 22:09:57 +05:30
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Registers g_regs;
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2014-04-05 10:53:51 +05:30
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u64 g_last_ticks = 0; ///< Last CPU ticks
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2014-04-27 22:09:57 +05:30
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/**
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* Sets whether the framebuffers are in the GSP heap (FCRAM) or VRAM
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* @param
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*/
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void SetFramebufferLocation(const FramebufferLocation mode) {
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switch (mode) {
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case FRAMEBUFFER_LOCATION_FCRAM:
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g_regs.framebuffer_top_left_1 = PADDR_TOP_LEFT_FRAME1;
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g_regs.framebuffer_top_left_2 = PADDR_TOP_LEFT_FRAME2;
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g_regs.framebuffer_top_right_1 = PADDR_TOP_RIGHT_FRAME1;
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g_regs.framebuffer_top_right_2 = PADDR_TOP_RIGHT_FRAME2;
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g_regs.framebuffer_sub_left_1 = PADDR_SUB_FRAME1;
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//g_regs.framebuffer_sub_left_2 = unknown;
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g_regs.framebuffer_sub_right_1 = PADDR_SUB_FRAME2;
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//g_regs.framebufferr_sub_right_2 = unknown;
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break;
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case FRAMEBUFFER_LOCATION_VRAM:
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g_regs.framebuffer_top_left_1 = PADDR_VRAM_TOP_LEFT_FRAME1;
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g_regs.framebuffer_top_left_2 = PADDR_VRAM_TOP_LEFT_FRAME2;
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g_regs.framebuffer_top_right_1 = PADDR_VRAM_TOP_RIGHT_FRAME1;
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g_regs.framebuffer_top_right_2 = PADDR_VRAM_TOP_RIGHT_FRAME2;
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g_regs.framebuffer_sub_left_1 = PADDR_VRAM_SUB_FRAME1;
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//g_regs.framebuffer_sub_left_2 = unknown;
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g_regs.framebuffer_sub_right_1 = PADDR_VRAM_SUB_FRAME2;
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//g_regs.framebufferr_sub_right_2 = unknown;
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break;
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}
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}
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/**
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* Gets the location of the framebuffers
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* @return Location of framebuffers as FramebufferLocation enum
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*/
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2014-07-11 22:59:12 +05:30
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FramebufferLocation GetFramebufferLocation(u32 address) {
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if ((address & ~Memory::VRAM_MASK) == Memory::VRAM_PADDR) {
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2014-04-27 22:09:57 +05:30
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return FRAMEBUFFER_LOCATION_VRAM;
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2014-07-11 22:59:12 +05:30
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} else if ((address & ~Memory::FCRAM_MASK) == Memory::FCRAM_PADDR) {
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2014-04-27 22:09:57 +05:30
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return FRAMEBUFFER_LOCATION_FCRAM;
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} else {
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2014-05-18 02:20:33 +05:30
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ERROR_LOG(GPU, "unknown framebuffer location!");
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2014-04-27 22:09:57 +05:30
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}
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return FRAMEBUFFER_LOCATION_UNKNOWN;
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}
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2014-07-11 22:59:12 +05:30
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u32 GetFramebufferAddr(const u32 address) {
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switch (GetFramebufferLocation(address)) {
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case FRAMEBUFFER_LOCATION_FCRAM:
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return Memory::VirtualAddressFromPhysical_FCRAM(address);
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case FRAMEBUFFER_LOCATION_VRAM:
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return Memory::VirtualAddressFromPhysical_VRAM(address);
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default:
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ERROR_LOG(GPU, "unknown framebuffer location");
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}
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return 0;
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}
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2014-04-27 22:09:57 +05:30
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/**
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* Gets a read-only pointer to a framebuffer in memory
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* @param address Physical address of framebuffer
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* @return Returns const pointer to raw framebuffer
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*/
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const u8* GetFramebufferPointer(const u32 address) {
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2014-07-11 22:59:12 +05:30
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u32 addr = GetFramebufferAddr(address);
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return (addr != 0) ? Memory::GetPointer(addr) : nullptr;
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2014-04-27 22:09:57 +05:30
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}
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2014-04-05 10:53:51 +05:30
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template <typename T>
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inline void Read(T &var, const u32 addr) {
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2014-04-27 22:09:57 +05:30
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switch (addr) {
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2014-06-04 22:00:23 +05:30
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case Registers::MemoryFillStart1:
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case Registers::MemoryFillStart2:
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var = g_regs.memory_fill[(addr - Registers::MemoryFillStart1) / 0x10].address_start;
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break;
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case Registers::MemoryFillEnd1:
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case Registers::MemoryFillEnd2:
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var = g_regs.memory_fill[(addr - Registers::MemoryFillEnd1) / 0x10].address_end;
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break;
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case Registers::MemoryFillSize1:
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case Registers::MemoryFillSize2:
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var = g_regs.memory_fill[(addr - Registers::MemoryFillSize1) / 0x10].size;
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break;
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case Registers::MemoryFillValue1:
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case Registers::MemoryFillValue2:
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var = g_regs.memory_fill[(addr - Registers::MemoryFillValue1) / 0x10].value;
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break;
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2014-07-11 22:40:08 +05:30
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case Registers::FramebufferTopSize:
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var = g_regs.top_framebuffer.size;
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break;
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2014-05-18 02:31:58 +05:30
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case Registers::FramebufferTopLeft1:
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2014-04-27 22:09:57 +05:30
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var = g_regs.framebuffer_top_left_1;
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break;
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2014-05-18 01:37:06 +05:30
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2014-05-18 02:31:58 +05:30
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case Registers::FramebufferTopLeft2:
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2014-04-27 22:09:57 +05:30
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var = g_regs.framebuffer_top_left_2;
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break;
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2014-05-18 01:37:06 +05:30
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2014-07-11 22:40:08 +05:30
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case Registers::FramebufferTopFormat:
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var = g_regs.top_framebuffer.format;
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break;
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case Registers::FramebufferTopSwapBuffers:
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var = g_regs.top_framebuffer.active_fb;
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break;
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case Registers::FramebufferTopStride:
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var = g_regs.top_framebuffer.stride;
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break;
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2014-05-18 02:31:58 +05:30
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case Registers::FramebufferTopRight1:
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2014-04-27 22:09:57 +05:30
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var = g_regs.framebuffer_top_right_1;
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break;
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2014-05-18 01:37:06 +05:30
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2014-05-18 02:31:58 +05:30
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case Registers::FramebufferTopRight2:
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2014-04-27 22:09:57 +05:30
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var = g_regs.framebuffer_top_right_2;
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break;
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2014-05-18 01:37:06 +05:30
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2014-07-11 22:40:08 +05:30
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case Registers::FramebufferSubSize:
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var = g_regs.sub_framebuffer.size;
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break;
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2014-05-18 02:31:58 +05:30
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case Registers::FramebufferSubLeft1:
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2014-04-27 22:09:57 +05:30
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var = g_regs.framebuffer_sub_left_1;
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break;
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2014-05-18 01:37:06 +05:30
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2014-05-18 02:31:58 +05:30
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case Registers::FramebufferSubRight1:
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2014-04-27 22:09:57 +05:30
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var = g_regs.framebuffer_sub_right_1;
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break;
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2014-05-18 01:37:06 +05:30
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2014-07-11 22:40:08 +05:30
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case Registers::FramebufferSubFormat:
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var = g_regs.sub_framebuffer.format;
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break;
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case Registers::FramebufferSubSwapBuffers:
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var = g_regs.sub_framebuffer.active_fb;
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break;
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case Registers::FramebufferSubStride:
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var = g_regs.sub_framebuffer.stride;
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break;
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case Registers::FramebufferSubLeft2:
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var = g_regs.framebuffer_sub_left_2;
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break;
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case Registers::FramebufferSubRight2:
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var = g_regs.framebuffer_sub_right_2;
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break;
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2014-06-01 03:38:00 +05:30
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case Registers::DisplayInputBufferAddr:
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var = g_regs.display_transfer.input_address;
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break;
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case Registers::DisplayOutputBufferAddr:
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var = g_regs.display_transfer.output_address;
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break;
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case Registers::DisplayOutputBufferSize:
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var = g_regs.display_transfer.output_size;
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break;
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case Registers::DisplayInputBufferSize:
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var = g_regs.display_transfer.input_size;
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break;
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case Registers::DisplayTransferFlags:
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var = g_regs.display_transfer.flags;
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break;
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// Not sure if this is supposed to be readable
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case Registers::DisplayTriggerTransfer:
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var = g_regs.display_transfer.trigger;
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break;
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2014-05-18 02:31:58 +05:30
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case Registers::CommandListSize:
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2014-05-18 01:37:06 +05:30
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var = g_regs.command_list_size;
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break;
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2014-05-18 02:31:58 +05:30
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case Registers::CommandListAddress:
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2014-05-18 01:37:06 +05:30
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var = g_regs.command_list_address;
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break;
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2014-05-18 02:31:58 +05:30
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case Registers::ProcessCommandList:
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2014-05-18 01:37:06 +05:30
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var = g_regs.command_processing_enabled;
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break;
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2014-04-27 22:09:57 +05:30
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default:
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2014-05-18 02:20:33 +05:30
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ERROR_LOG(GPU, "unknown Read%d @ 0x%08X", sizeof(var) * 8, addr);
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2014-04-27 22:09:57 +05:30
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break;
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}
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2014-04-05 10:53:51 +05:30
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}
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template <typename T>
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inline void Write(u32 addr, const T data) {
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2014-05-18 02:31:58 +05:30
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switch (static_cast<Registers::Id>(addr)) {
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2014-06-04 22:00:23 +05:30
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case Registers::MemoryFillStart1:
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case Registers::MemoryFillStart2:
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g_regs.memory_fill[(addr - Registers::MemoryFillStart1) / 0x10].address_start = data;
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break;
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case Registers::MemoryFillEnd1:
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case Registers::MemoryFillEnd2:
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g_regs.memory_fill[(addr - Registers::MemoryFillEnd1) / 0x10].address_end = data;
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break;
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case Registers::MemoryFillSize1:
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case Registers::MemoryFillSize2:
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g_regs.memory_fill[(addr - Registers::MemoryFillSize1) / 0x10].size = data;
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break;
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case Registers::MemoryFillValue1:
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case Registers::MemoryFillValue2:
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{
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Registers::MemoryFillConfig& config = g_regs.memory_fill[(addr - Registers::MemoryFillValue1) / 0x10];
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config.value = data;
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// TODO: Not sure if this check should be done at GSP level instead
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if (config.address_start) {
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// TODO: Not sure if this algorithm is correct, particularly because it doesn't use the size member at all
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u32* start = (u32*)Memory::GetPointer(config.GetStartAddress());
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u32* end = (u32*)Memory::GetPointer(config.GetEndAddress());
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for (u32* ptr = start; ptr < end; ++ptr)
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*ptr = bswap32(config.value); // TODO: This is just a workaround to missing framebuffer format emulation
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DEBUG_LOG(GPU, "MemoryFill from %x to %x", config.GetStartAddress(), config.GetEndAddress());
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}
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break;
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}
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2014-07-11 22:40:08 +05:30
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// TODO: Framebuffer registers!!
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case Registers::FramebufferTopSwapBuffers:
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g_regs.top_framebuffer.active_fb = data;
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// TODO: Not sure if this should only be done upon a change!
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break;
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case Registers::FramebufferSubSwapBuffers:
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g_regs.sub_framebuffer.active_fb = data;
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// TODO: Not sure if this should only be done upon a change!
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break;
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2014-06-01 03:38:00 +05:30
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case Registers::DisplayInputBufferAddr:
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g_regs.display_transfer.input_address = data;
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break;
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case Registers::DisplayOutputBufferAddr:
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g_regs.display_transfer.output_address = data;
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break;
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case Registers::DisplayOutputBufferSize:
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g_regs.display_transfer.output_size = data;
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break;
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case Registers::DisplayInputBufferSize:
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g_regs.display_transfer.input_size = data;
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break;
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case Registers::DisplayTransferFlags:
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g_regs.display_transfer.flags = data;
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break;
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case Registers::DisplayTriggerTransfer:
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g_regs.display_transfer.trigger = data;
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if (g_regs.display_transfer.trigger & 1) {
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2014-07-11 22:31:14 +05:30
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u8* source_pointer = Memory::GetPointer(g_regs.display_transfer.GetPhysicalInputAddress());
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u8* dest_pointer = Memory::GetPointer(g_regs.display_transfer.GetPhysicalOutputAddress());
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for (int y = 0; y < g_regs.display_transfer.output_height; ++y) {
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2014-07-11 23:18:01 +05:30
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// TODO: Why does the register seem to hold twice the framebuffer width?
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for (int x = 0; x < g_regs.display_transfer.output_width / 2; ++x) {
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int source[4] = { 0, 0, 0, 0}; // rgba;
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switch (g_regs.display_transfer.input_format) {
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case Registers::FramebufferFormat::RGBA8:
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{
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// TODO: Most likely got the component order messed up.
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u8* srcptr = source_pointer + x * 4 + y * g_regs.display_transfer.input_width * 4 / 2;
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source[0] = srcptr[0]; // blue
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source[1] = srcptr[1]; // green
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source[2] = srcptr[2]; // red
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source[3] = srcptr[3]; // alpha
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break;
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}
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default:
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ERROR_LOG(GPU, "Unknown source framebuffer format %x", (int)g_regs.display_transfer.input_format.Value());
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break;
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}
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switch (g_regs.display_transfer.output_format) {
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/*case Registers::FramebufferFormat::RGBA8:
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{
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// TODO: Untested
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u8* dstptr = (u32*)(dest_pointer + x * 4 + y * g_regs.display_transfer.output_width * 4);
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dstptr[0] = source[0];
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|
|
dstptr[1] = source[1];
|
|
|
|
dstptr[2] = source[2];
|
|
|
|
dstptr[3] = source[3];
|
|
|
|
break;
|
|
|
|
}*/
|
|
|
|
|
|
|
|
case Registers::FramebufferFormat::RGB8:
|
|
|
|
{
|
|
|
|
u8* dstptr = dest_pointer + x * 3 + y * g_regs.display_transfer.output_width * 3 / 2;
|
|
|
|
dstptr[0] = source[0]; // blue
|
|
|
|
dstptr[1] = source[1]; // green
|
|
|
|
dstptr[2] = source[2]; // red
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
default:
|
|
|
|
ERROR_LOG(GPU, "Unknown destination framebuffer format %x", static_cast<int>(g_regs.display_transfer.output_format.Value()));
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
2014-07-11 22:31:14 +05:30
|
|
|
}
|
|
|
|
|
|
|
|
DEBUG_LOG(GPU, "DisplayTriggerTransfer: %x bytes from %x(%xx%x)-> %x(%xx%x), dst format %x",
|
|
|
|
g_regs.display_transfer.output_height * g_regs.display_transfer.output_width * 4,
|
|
|
|
g_regs.display_transfer.GetPhysicalInputAddress(), (int)g_regs.display_transfer.input_width, (int)g_regs.display_transfer.input_height,
|
|
|
|
g_regs.display_transfer.GetPhysicalOutputAddress(), (int)g_regs.display_transfer.output_width, (int)g_regs.display_transfer.output_height,
|
2014-07-11 22:40:08 +05:30
|
|
|
(int)g_regs.display_transfer.output_format.Value());
|
2014-06-01 03:38:00 +05:30
|
|
|
}
|
|
|
|
break;
|
|
|
|
|
2014-05-18 02:31:58 +05:30
|
|
|
case Registers::CommandListSize:
|
2014-05-18 01:37:06 +05:30
|
|
|
g_regs.command_list_size = data;
|
|
|
|
break;
|
|
|
|
|
2014-05-18 02:31:58 +05:30
|
|
|
case Registers::CommandListAddress:
|
2014-05-18 01:37:06 +05:30
|
|
|
g_regs.command_list_address = data;
|
|
|
|
break;
|
|
|
|
|
2014-05-18 02:31:58 +05:30
|
|
|
case Registers::ProcessCommandList:
|
2014-05-18 01:37:06 +05:30
|
|
|
g_regs.command_processing_enabled = data;
|
|
|
|
if (g_regs.command_processing_enabled & 1)
|
|
|
|
{
|
|
|
|
// u32* buffer = (u32*)Memory::GetPointer(g_regs.command_list_address << 3);
|
2014-05-18 02:20:33 +05:30
|
|
|
ERROR_LOG(GPU, "Beginning %x bytes of commands from address %x", g_regs.command_list_size, g_regs.command_list_address << 3);
|
2014-05-18 01:37:06 +05:30
|
|
|
// TODO: Process command list!
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
|
|
|
|
default:
|
2014-05-18 02:20:33 +05:30
|
|
|
ERROR_LOG(GPU, "unknown Write%d 0x%08X @ 0x%08X", sizeof(data) * 8, data, addr);
|
2014-05-18 01:37:06 +05:30
|
|
|
break;
|
|
|
|
}
|
2014-04-05 10:53:51 +05:30
|
|
|
}
|
|
|
|
|
2014-04-26 23:51:40 +05:30
|
|
|
// Explicitly instantiate template functions because we aren't defining this in the header:
|
|
|
|
|
|
|
|
template void Read<u64>(u64 &var, const u32 addr);
|
|
|
|
template void Read<u32>(u32 &var, const u32 addr);
|
|
|
|
template void Read<u16>(u16 &var, const u32 addr);
|
|
|
|
template void Read<u8>(u8 &var, const u32 addr);
|
|
|
|
|
|
|
|
template void Write<u64>(u32 addr, const u64 data);
|
|
|
|
template void Write<u32>(u32 addr, const u32 data);
|
|
|
|
template void Write<u16>(u32 addr, const u16 data);
|
|
|
|
template void Write<u8>(u32 addr, const u8 data);
|
|
|
|
|
2014-04-05 10:53:51 +05:30
|
|
|
/// Update hardware
|
|
|
|
void Update() {
|
2014-04-06 00:53:59 +05:30
|
|
|
u64 current_ticks = Core::g_app_core->GetTicks();
|
2014-04-05 10:53:51 +05:30
|
|
|
|
2014-05-23 05:31:04 +05:30
|
|
|
// Fake a vertical blank
|
2014-04-05 10:53:51 +05:30
|
|
|
if ((current_ticks - g_last_ticks) >= kFrameTicks) {
|
|
|
|
g_last_ticks = current_ticks;
|
2014-04-07 02:26:13 +05:30
|
|
|
VideoCore::g_renderer->SwapBuffers();
|
2014-05-23 05:31:04 +05:30
|
|
|
Kernel::WaitCurrentThread(WAITTYPE_VBLANK);
|
2014-04-05 10:53:51 +05:30
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/// Initialize hardware
|
|
|
|
void Init() {
|
2014-04-06 00:53:59 +05:30
|
|
|
g_last_ticks = Core::g_app_core->GetTicks();
|
2014-07-11 22:44:15 +05:30
|
|
|
// SetFramebufferLocation(FRAMEBUFFER_LOCATION_FCRAM);
|
|
|
|
SetFramebufferLocation(FRAMEBUFFER_LOCATION_VRAM);
|
|
|
|
|
|
|
|
// TODO: Width should be 240 instead?
|
|
|
|
g_regs.top_framebuffer.width = 480;
|
|
|
|
g_regs.top_framebuffer.height = 400;
|
|
|
|
g_regs.top_framebuffer.stride = 480*3;
|
|
|
|
g_regs.top_framebuffer.color_format = Registers::FramebufferFormat::RGB8;
|
|
|
|
g_regs.top_framebuffer.active_fb = 0;
|
|
|
|
|
|
|
|
g_regs.sub_framebuffer.width = 480;
|
|
|
|
g_regs.sub_framebuffer.height = 400;
|
|
|
|
g_regs.sub_framebuffer.stride = 480*3;
|
|
|
|
g_regs.sub_framebuffer.color_format = Registers::FramebufferFormat::RGB8;
|
|
|
|
g_regs.sub_framebuffer.active_fb = 0;
|
|
|
|
|
2014-05-18 02:20:33 +05:30
|
|
|
NOTICE_LOG(GPU, "initialized OK");
|
2014-04-05 10:53:51 +05:30
|
|
|
}
|
|
|
|
|
|
|
|
/// Shutdown hardware
|
|
|
|
void Shutdown() {
|
2014-05-18 02:20:33 +05:30
|
|
|
NOTICE_LOG(GPU, "shutdown OK");
|
2014-04-05 10:53:51 +05:30
|
|
|
}
|
|
|
|
|
|
|
|
} // namespace
|