2013-09-18 08:33:54 +05:30
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/*
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armmmu.c - Memory Management Unit emulation.
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ARMulator extensions for the ARM7100 family.
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Copyright (C) 1999 Ben Williamson
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <assert.h>
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#include <string.h>
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#include "armdefs.h"
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/* two header for arm disassemble */
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//#include "skyeye_arch.h"
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#include "armcpu.h"
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extern mmu_ops_t xscale_mmu_ops;
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exception_t arm_mmu_write(short size, u32 addr, uint32_t *value);
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exception_t arm_mmu_read(short size, u32 addr, uint32_t *value);
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#define MMU_OPS (state->mmu.ops)
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ARMword skyeye_cachetype = -1;
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int
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mmu_init (ARMul_State * state)
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{
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int ret;
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state->mmu.control = 0x70;
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state->mmu.translation_table_base = 0xDEADC0DE;
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state->mmu.domain_access_control = 0xDEADC0DE;
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state->mmu.fault_status = 0;
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state->mmu.fault_address = 0;
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state->mmu.process_id = 0;
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switch (state->cpu->cpu_val & state->cpu->cpu_mask) {
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2014-03-30 07:23:07 +05:30
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//case SA1100:
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//case SA1110:
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// NOTICE_LOG(ARM11, "SKYEYE: use sa11xx mmu ops\n");
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// state->mmu.ops = sa_mmu_ops;
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// break;
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//case PXA250:
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//case PXA270: //xscale
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// NOTICE_LOG(ARM11, "SKYEYE: use xscale mmu ops\n");
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// state->mmu.ops = xscale_mmu_ops;
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// break;
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//case 0x41807200: //arm720t
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//case 0x41007700: //arm7tdmi
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//case 0x41007100: //arm7100
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// NOTICE_LOG(ARM11, "SKYEYE: use arm7100 mmu ops\n");
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// state->mmu.ops = arm7100_mmu_ops;
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// break;
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//case 0x41009200:
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// NOTICE_LOG(ARM11, "SKYEYE: use arm920t mmu ops\n");
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// state->mmu.ops = arm920t_mmu_ops;
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// break;
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//case 0x41069260:
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// NOTICE_LOG(ARM11, "SKYEYE: use arm926ejs mmu ops\n");
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// state->mmu.ops = arm926ejs_mmu_ops;
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// break;
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2013-09-18 08:33:54 +05:30
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/* case 0x560f5810: */
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case 0x0007b000:
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2014-03-30 07:23:07 +05:30
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NOTICE_LOG(ARM11, "SKYEYE: use arm11jzf-s mmu ops\n");
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2014-03-30 08:58:38 +05:30
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state->mmu.ops = arm1176jzf_s_mmu_ops;
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2013-09-18 08:33:54 +05:30
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break;
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default:
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2014-03-30 07:23:07 +05:30
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ERROR_LOG (ARM11,
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2013-09-18 08:33:54 +05:30
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"SKYEYE: armmmu.c : mmu_init: unknown cpu_val&cpu_mask 0x%x\n",
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state->cpu->cpu_val & state->cpu->cpu_mask);
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break;
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};
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ret = state->mmu.ops.init (state);
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state->mmu_inited = (ret == 0);
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/* initialize mmu_read and mmu_write for disassemble */
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2014-03-30 07:23:07 +05:30
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//skyeye_config_t *config = get_current_config();
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//generic_arch_t *arch_instance = get_arch_instance(config->arch->arch_name);
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//arch_instance->mmu_read = arm_mmu_read;
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//arch_instance->mmu_write = arm_mmu_write;
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2013-09-18 08:33:54 +05:30
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return ret;
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}
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int
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mmu_reset (ARMul_State * state)
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{
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if (state->mmu_inited)
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mmu_exit (state);
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return mmu_init (state);
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}
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void
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mmu_exit (ARMul_State * state)
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{
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MMU_OPS.exit (state);
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state->mmu_inited = 0;
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}
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fault_t
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mmu_read_byte (ARMul_State * state, ARMword virt_addr, ARMword * data)
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{
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return MMU_OPS.read_byte (state, virt_addr, data);
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};
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fault_t
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mmu_read_halfword (ARMul_State * state, ARMword virt_addr, ARMword * data)
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{
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return MMU_OPS.read_halfword (state, virt_addr, data);
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};
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fault_t
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mmu_read_word (ARMul_State * state, ARMword virt_addr, ARMword * data)
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{
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return MMU_OPS.read_word (state, virt_addr, data);
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};
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fault_t
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mmu_write_byte (ARMul_State * state, ARMword virt_addr, ARMword data)
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{
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fault_t fault;
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//static int count = 0;
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//count ++;
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fault = MMU_OPS.write_byte (state, virt_addr, data);
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return fault;
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}
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fault_t
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mmu_write_halfword (ARMul_State * state, ARMword virt_addr, ARMword data)
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{
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fault_t fault;
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//static int count = 0;
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//count ++;
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fault = MMU_OPS.write_halfword (state, virt_addr, data);
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return fault;
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}
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fault_t
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mmu_write_word (ARMul_State * state, ARMword virt_addr, ARMword data)
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{
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fault_t fault;
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fault = MMU_OPS.write_word (state, virt_addr, data);
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/*used for debug for MMU*
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if (!fault){
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ARMword tmp;
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if (mmu_read_word(state, virt_addr, &tmp)){
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err_msg("load back\n");
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exit(-1);
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}else{
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if (tmp != data){
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err_msg("load back not equal %d %x\n", count, virt_addr);
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}
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}
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}
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*/
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return fault;
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};
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fault_t
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mmu_load_instr (ARMul_State * state, ARMword virt_addr, ARMword * instr)
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{
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return MMU_OPS.load_instr (state, virt_addr, instr);
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}
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ARMword
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mmu_mrc (ARMul_State * state, ARMword instr, ARMword * value)
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{
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return MMU_OPS.mrc (state, instr, value);
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}
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void
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mmu_mcr (ARMul_State * state, ARMword instr, ARMword value)
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{
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MMU_OPS.mcr (state, instr, value);
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}
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/*ywc 20050416*/
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int
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mmu_v2p_dbct (ARMul_State * state, ARMword virt_addr, ARMword * phys_addr)
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{
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return (MMU_OPS.v2p_dbct (state, virt_addr, phys_addr));
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}
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2014-03-30 07:23:07 +05:30
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//
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//
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///* dis_mmu_read for disassemble */
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//exception_t arm_mmu_read(short size, uint32_t addr, uint32_t * value)
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//{
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// ARMul_State *state;
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// ARM_CPU_State *cpu = get_current_cpu();
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// state = &cpu->core[0];
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// switch(size){
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// case 8:
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// MMU_OPS.read_byte (state, addr, value);
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// break;
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// case 16:
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// case 32:
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// break;
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// default:
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// ERROR_LOG(ARM11, "Error size %d", size);
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// break;
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// }
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// return No_exp;
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//}
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///* dis_mmu_write for disassemble */
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//exception_t arm_mmu_write(short size, uint32_t addr, uint32_t *value)
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//{
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// ARMul_State *state;
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// ARM_CPU_State *cpu = get_current_cpu();
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// state = &cpu->core[0];
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// switch(size){
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// case 8:
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// MMU_OPS.write_byte (state, addr, value);
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// break;
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// case 16:
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// case 32:
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// break;
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// default:
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// printf("In %s error size %d Line %d\n", __func__, size, __LINE__);
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// break;
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// }
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// return No_exp;
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//}
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