hacked CPU interpreter to ignore branch on SVC instruction (as we are HLEing this...)
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@ -530,9 +530,13 @@ ARMul_Abort (ARMul_State * state, ARMword vector)
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isize);
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isize);
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break;
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break;
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case ARMul_SWIV: /* Software Interrupt */
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case ARMul_SWIV: /* Software Interrupt */
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SETABORT (IBIT, state->prog32Sig ? SVC32MODE : SVC26MODE,
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// Modified SETABORT that doesn't branch to a SVC vector as we are implementing this in HLE
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// Instead of doing normal routine, backup R15 by one instruction (this is what PC will get
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// set to, making it the next instruction after the SVC call), and skip setting the LR.
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SETABORT_SKIPBRANCH (IBIT, state->prog32Sig ? SVC32MODE : SVC26MODE,
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isize);
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isize);
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break;
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state->Reg[15] -= 4;
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return;
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case ARMul_PrefetchAbortV: /* Prefetch Abort */
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case ARMul_PrefetchAbortV: /* Prefetch Abort */
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state->AbortAddr = 1;
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state->AbortAddr = 1;
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SETABORT (IBIT, state->prog32Sig ? ABORT32MODE : SVC26MODE,
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SETABORT (IBIT, state->prog32Sig ? ABORT32MODE : SVC26MODE,
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