Merge pull request #822 from bunnei/pica-improvements
Pica improvements
This commit is contained in:
bunnei
commit
8852fc6a87
@ -56,7 +56,17 @@ static inline void WritePicaReg(u32 id, u32 value, u32 mask) {
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// Trigger IRQ
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case PICA_REG_INDEX(trigger_irq):
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GSP_GPU::SignalInterrupt(GSP_GPU::InterruptId::P3D);
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return;
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break;
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case PICA_REG_INDEX_WORKAROUND(command_buffer.trigger[0], 0x23c):
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case PICA_REG_INDEX_WORKAROUND(command_buffer.trigger[1], 0x23d):
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{
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unsigned index = id - PICA_REG_INDEX(command_buffer.trigger[0]);
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u32* head_ptr = (u32*)Memory::GetPhysicalPointer(regs.command_buffer.GetPhysicalAddress(index));
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g_state.cmd_list.head_ptr = g_state.cmd_list.current_ptr = head_ptr;
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g_state.cmd_list.length = regs.command_buffer.GetSize(index) / sizeof(u32);
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break;
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}
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// It seems like these trigger vertex rendering
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case PICA_REG_INDEX(trigger_draw):
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@ -363,38 +373,34 @@ static inline void WritePicaReg(u32 id, u32 value, u32 mask) {
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g_debug_context->OnEvent(DebugContext::Event::CommandProcessed, reinterpret_cast<void*>(&id));
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}
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static std::ptrdiff_t ExecuteCommandBlock(const u32* first_command_word) {
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const CommandHeader& header = *(const CommandHeader*)(&first_command_word[1]);
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u32* read_pointer = (u32*)first_command_word;
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const u32 write_mask = ((header.parameter_mask & 0x1) ? (0xFFu << 0) : 0u) |
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((header.parameter_mask & 0x2) ? (0xFFu << 8) : 0u) |
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((header.parameter_mask & 0x4) ? (0xFFu << 16) : 0u) |
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((header.parameter_mask & 0x8) ? (0xFFu << 24) : 0u);
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WritePicaReg(header.cmd_id, *read_pointer, write_mask);
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read_pointer += 2;
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for (unsigned int i = 1; i < 1+header.extra_data_length; ++i) {
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u32 cmd = header.cmd_id + ((header.group_commands) ? i : 0);
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WritePicaReg(cmd, *read_pointer, write_mask);
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++read_pointer;
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}
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// align read pointer to 8 bytes
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if ((first_command_word - read_pointer) % 2)
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++read_pointer;
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return read_pointer - first_command_word;
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}
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void ProcessCommandList(const u32* list, u32 size) {
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u32* read_pointer = (u32*)list;
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u32 list_length = size / sizeof(u32);
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g_state.cmd_list.head_ptr = g_state.cmd_list.current_ptr = list;
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g_state.cmd_list.length = size / sizeof(u32);
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while (read_pointer < list + list_length) {
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read_pointer += ExecuteCommandBlock(read_pointer);
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while (g_state.cmd_list.current_ptr < g_state.cmd_list.head_ptr + g_state.cmd_list.length) {
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// Expand a 4-bit mask to 4-byte mask, e.g. 0b0101 -> 0x00FF00FF
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static const u32 expand_bits_to_bytes[] = {
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0x00000000, 0x000000ff, 0x0000ff00, 0x0000ffff,
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0x00ff0000, 0x00ff00ff, 0x00ffff00, 0x00ffffff,
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0xff000000, 0xff0000ff, 0xff00ff00, 0xff00ffff,
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0xffff0000, 0xffff00ff, 0xffffff00, 0xffffffff
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};
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// Align read pointer to 8 bytes
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if ((g_state.cmd_list.head_ptr - g_state.cmd_list.current_ptr) % 2 != 0)
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++g_state.cmd_list.current_ptr;
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u32 value = *g_state.cmd_list.current_ptr++;
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const CommandHeader header = { *g_state.cmd_list.current_ptr++ };
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const u32 write_mask = expand_bits_to_bytes[header.parameter_mask];
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u32 cmd = header.cmd_id;
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WritePicaReg(cmd, value, write_mask);
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for (unsigned i = 0; i < header.extra_data_length; ++i) {
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u32 cmd = header.cmd_id + (header.group_commands ? i + 1 : 0);
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WritePicaReg(cmd, *g_state.cmd_list.current_ptr++, write_mask);
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}
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}
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}
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@ -162,6 +162,25 @@ struct Regs {
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ETC1A4 = 13, // compressed
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};
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enum class LogicOp : u32 {
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Clear = 0,
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And = 1,
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AndReverse = 2,
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Copy = 3,
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Set = 4,
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CopyInverted = 5,
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NoOp = 6,
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Invert = 7,
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Nand = 8,
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Or = 9,
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Nor = 10,
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Xor = 11,
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Equiv = 12,
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AndInverted = 13,
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OrReverse = 14,
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OrInverted = 15,
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};
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static unsigned NibblesPerPixel(TextureFormat format) {
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switch (format) {
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case TextureFormat::RGBA8:
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@ -221,6 +240,7 @@ struct Regs {
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enum class Source : u32 {
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PrimaryColor = 0x0,
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PrimaryFragmentColor = 0x1,
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SecondaryFragmentColor = 0x2,
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Texture0 = 0x3,
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Texture1 = 0x4,
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@ -413,13 +433,9 @@ struct Regs {
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} alpha_blending;
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union {
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enum Op {
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Set = 4,
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BitField<0, 4, LogicOp> logic_op;
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};
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BitField<0, 4, Op> op;
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} logic_op;
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union {
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BitField< 0, 8, u32> r;
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BitField< 8, 8, u32> g;
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@ -708,7 +724,33 @@ struct Regs {
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u32 set_value[3];
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} vs_default_attributes_setup;
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INSERT_PADDING_WORDS(0x28);
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INSERT_PADDING_WORDS(0x2);
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struct {
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// There are two channels that can be used to configure the next command buffer, which
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// can be then executed by writing to the "trigger" registers. There are two reasons why a
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// game might use this feature:
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// 1) With this, an arbitrary number of additional command buffers may be executed in
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// sequence without requiring any intervention of the CPU after the initial one is
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// kicked off.
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// 2) Games can configure these registers to provide a command list subroutine mechanism.
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BitField< 0, 20, u32> size[2]; ///< Size (in bytes / 8) of each channel's command buffer
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BitField< 0, 28, u32> addr[2]; ///< Physical address / 8 of each channel's command buffer
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u32 trigger[2]; ///< Triggers execution of the channel's command buffer when written to
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unsigned GetSize(unsigned index) const {
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ASSERT(index < 2);
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return 8 * size[index];
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}
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PAddr GetPhysicalAddress(unsigned index) const {
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ASSERT(index < 2);
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return (PAddr)(8 * addr[index]);
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}
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} command_buffer;
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INSERT_PADDING_WORDS(0x20);
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enum class TriangleTopology : u32 {
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List = 0,
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@ -861,6 +903,7 @@ struct Regs {
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ADD_FIELD(trigger_draw);
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ADD_FIELD(trigger_draw_indexed);
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ADD_FIELD(vs_default_attributes_setup);
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ADD_FIELD(command_buffer);
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ADD_FIELD(triangle_topology);
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ADD_FIELD(vs_bool_uniforms);
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ADD_FIELD(vs_int_uniforms);
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@ -938,6 +981,7 @@ ASSERT_REG_POSITION(num_vertices, 0x228);
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ASSERT_REG_POSITION(trigger_draw, 0x22e);
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ASSERT_REG_POSITION(trigger_draw_indexed, 0x22f);
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ASSERT_REG_POSITION(vs_default_attributes_setup, 0x232);
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ASSERT_REG_POSITION(command_buffer, 0x238);
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ASSERT_REG_POSITION(triangle_topology, 0x25e);
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ASSERT_REG_POSITION(vs_bool_uniforms, 0x2b0);
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ASSERT_REG_POSITION(vs_int_uniforms, 0x2b1);
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@ -1053,21 +1097,12 @@ private:
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float value;
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};
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union CommandHeader {
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CommandHeader(u32 h) : hex(h) {}
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u32 hex;
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BitField< 0, 16, u32> cmd_id;
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BitField<16, 4, u32> parameter_mask;
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BitField<20, 11, u32> extra_data_length;
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BitField<31, 1, u32> group_commands;
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};
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/// Struct used to describe current Pica state
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struct State {
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/// Pica registers
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Regs regs;
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/// Vertex shader memory
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struct {
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struct {
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Math::Vec4<float24> f[96];
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@ -1080,6 +1115,13 @@ struct State {
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std::array<u32, 1024> program_code;
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std::array<u32, 1024> swizzle_data;
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} vs;
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/// Current Pica command list
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struct {
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const u32* head_ptr;
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const u32* current_ptr;
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u32 length;
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} cmd_list;
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};
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/// Initialize Pica state
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@ -402,11 +402,16 @@ static void ProcessTriangleInternal(const VertexShader::OutputVertex& v0,
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auto GetSource = [&](Source source) -> Math::Vec4<u8> {
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switch (source) {
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// TODO: What's the difference between these two?
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case Source::PrimaryColor:
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// HACK: Until we implement fragment lighting, use primary_color
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case Source::PrimaryFragmentColor:
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return primary_color;
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// HACK: Until we implement fragment lighting, use zero
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case Source::SecondaryFragmentColor:
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return {0, 0, 0, 0};
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case Source::Texture0:
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return texture_color[0];
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@ -570,6 +575,13 @@ static void ProcessTriangleInternal(const VertexShader::OutputVertex& v0,
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case Operation::Add:
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return std::min(255, input[0] + input[1]);
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case Operation::AddSigned:
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{
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// TODO(bunnei): Verify that the color conversion from (float) 0.5f to (byte) 128 is correct
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auto result = static_cast<int>(input[0]) + static_cast<int>(input[1]) - 128;
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return static_cast<u8>(MathUtil::Clamp<int>(result, 0, 255));
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}
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case Operation::Lerp:
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return (input[0] * input[2] + input[1] * (255 - input[2])) / 255;
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@ -808,10 +820,9 @@ static void ProcessTriangleInternal(const VertexShader::OutputVertex& v0,
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}
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};
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using BlendEquation = Regs::BlendEquation;
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static auto EvaluateBlendEquation = [](const Math::Vec4<u8>& src, const Math::Vec4<u8>& srcfactor,
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const Math::Vec4<u8>& dest, const Math::Vec4<u8>& destfactor,
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BlendEquation equation) {
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Regs::BlendEquation equation) {
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Math::Vec4<int> result;
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auto src_result = (src * srcfactor).Cast<int>();
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@ -866,8 +877,63 @@ static void ProcessTriangleInternal(const VertexShader::OutputVertex& v0,
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blend_output = EvaluateBlendEquation(combiner_output, srcfactor, dest, dstfactor, params.blend_equation_rgb);
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blend_output.a() = EvaluateBlendEquation(combiner_output, srcfactor, dest, dstfactor, params.blend_equation_a).a();
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} else {
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LOG_CRITICAL(HW_GPU, "logic op: %x", output_merger.logic_op);
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UNIMPLEMENTED();
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static auto LogicOp = [](u8 src, u8 dest, Regs::LogicOp op) -> u8 {
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switch (op) {
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case Regs::LogicOp::Clear:
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return 0;
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case Regs::LogicOp::And:
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return src & dest;
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case Regs::LogicOp::AndReverse:
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return src & ~dest;
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case Regs::LogicOp::Copy:
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return src;
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case Regs::LogicOp::Set:
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return 255;
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case Regs::LogicOp::CopyInverted:
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return ~src;
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case Regs::LogicOp::NoOp:
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return dest;
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case Regs::LogicOp::Invert:
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return ~dest;
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case Regs::LogicOp::Nand:
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return ~(src & dest);
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case Regs::LogicOp::Or:
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return src | dest;
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case Regs::LogicOp::Nor:
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return ~(src | dest);
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case Regs::LogicOp::Xor:
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return src ^ dest;
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case Regs::LogicOp::Equiv:
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return ~(src ^ dest);
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case Regs::LogicOp::AndInverted:
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return ~src & dest;
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case Regs::LogicOp::OrReverse:
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return src | ~dest;
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case Regs::LogicOp::OrInverted:
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return ~src | dest;
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}
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};
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blend_output = Math::MakeVec(
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LogicOp(combiner_output.r(), dest.r(), output_merger.logic_op),
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LogicOp(combiner_output.g(), dest.g(), output_merger.logic_op),
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LogicOp(combiner_output.b(), dest.b(), output_merger.logic_op),
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LogicOp(combiner_output.a(), dest.a(), output_merger.logic_op));
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}
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const Math::Vec4<u8> result = {
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@ -135,6 +135,7 @@ void RasterizerOpenGL::Reset() {
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SyncBlendFuncs();
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SyncBlendColor();
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SyncAlphaTest();
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SyncLogicOp();
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SyncStencilTest();
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SyncDepthTest();
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@ -249,6 +250,11 @@ void RasterizerOpenGL::NotifyPicaRegisterChanged(u32 id) {
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SyncDepthTest();
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break;
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// Logic op
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case PICA_REG_INDEX(output_merger.logic_op):
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SyncLogicOp();
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break;
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// TEV stage 0
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case PICA_REG_INDEX(tev_stage0.color_source1):
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SyncTevSources(0, regs.tev_stage0);
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@ -633,6 +639,10 @@ void RasterizerOpenGL::SyncAlphaTest() {
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glUniform1f(uniform_alphatest_ref, regs.output_merger.alpha_test.ref / 255.0f);
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}
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void RasterizerOpenGL::SyncLogicOp() {
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state.logic_op = PicaToGL::LogicOp(Pica::g_state.regs.output_merger.logic_op);
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}
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void RasterizerOpenGL::SyncStencilTest() {
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// TODO: Implement stencil test, mask, and op
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}
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@ -125,6 +125,9 @@ private:
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/// Syncs the alpha test states to match the PICA register
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void SyncAlphaTest();
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/// Syncs the logic op states to match the PICA register
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void SyncLogicOp();
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/// Syncs the stencil test states to match the PICA register
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void SyncStencilTest();
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@ -71,6 +71,7 @@ const char g_fragment_shader_hw[] = R"(
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#define SOURCE_PRIMARYCOLOR 0x0
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#define SOURCE_PRIMARYFRAGMENTCOLOR 0x1
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#define SOURCE_SECONDARYFRAGMENTCOLOR 0x2
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#define SOURCE_TEXTURE0 0x3
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#define SOURCE_TEXTURE1 0x4
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#define SOURCE_TEXTURE2 0x5
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@ -151,8 +152,11 @@ vec4 GetSource(int source) {
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if (source == SOURCE_PRIMARYCOLOR) {
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return o[2];
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} else if (source == SOURCE_PRIMARYFRAGMENTCOLOR) {
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// HACK: Uses color value, but should really use fragment lighting output
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// HACK: Until we implement fragment lighting, use primary_color
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return o[2];
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} else if (source == SOURCE_SECONDARYFRAGMENTCOLOR) {
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// HACK: Until we implement fragment lighting, use zero
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return vec4(0.0, 0.0, 0.0, 0.0);
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} else if (source == SOURCE_TEXTURE0) {
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return texture(tex[0], o[3].xy);
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} else if (source == SOURCE_TEXTURE1) {
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@ -32,6 +32,8 @@ OpenGLState::OpenGLState() {
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blend.color.blue = 0.0f;
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blend.color.alpha = 0.0f;
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logic_op = GL_COPY;
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for (auto& texture_unit : texture_units) {
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texture_unit.enabled_2d = false;
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texture_unit.texture_2d = 0;
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@ -99,8 +101,13 @@ void OpenGLState::Apply() {
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if (blend.enabled != cur_state.blend.enabled) {
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if (blend.enabled) {
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glEnable(GL_BLEND);
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cur_state.logic_op = GL_COPY;
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glLogicOp(cur_state.logic_op);
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glDisable(GL_COLOR_LOGIC_OP);
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} else {
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glDisable(GL_BLEND);
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glEnable(GL_COLOR_LOGIC_OP);
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}
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}
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@ -118,6 +125,10 @@ void OpenGLState::Apply() {
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glBlendFuncSeparate(blend.src_rgb_func, blend.dst_rgb_func, blend.src_a_func, blend.dst_a_func);
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}
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if (logic_op != cur_state.logic_op) {
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glLogicOp(logic_op);
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}
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// Textures
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for (unsigned texture_index = 0; texture_index < ARRAY_SIZE(texture_units); ++texture_index) {
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if (texture_units[texture_index].enabled_2d != cur_state.texture_units[texture_index].enabled_2d) {
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@ -42,6 +42,8 @@ public:
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} color; // GL_BLEND_COLOR
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} blend;
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GLenum logic_op; // GL_LOGIC_OP_MODE
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// 3 texture units - one for each that is used in PICA fragment shader emulation
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struct {
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bool enabled_2d; // GL_TEXTURE_2D
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@ -71,6 +71,37 @@ inline GLenum BlendFunc(Pica::Regs::BlendFactor factor) {
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return blend_func_table[(unsigned)factor];
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}
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inline GLenum LogicOp(Pica::Regs::LogicOp op) {
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static const GLenum logic_op_table[] = {
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GL_CLEAR, // Clear
|
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GL_AND, // And
|
||||
GL_AND_REVERSE, // AndReverse
|
||||
GL_COPY, // Copy
|
||||
GL_SET, // Set
|
||||
GL_COPY_INVERTED, // CopyInverted
|
||||
GL_NOOP, // NoOp
|
||||
GL_INVERT, // Invert
|
||||
GL_NAND, // Nand
|
||||
GL_OR, // Or
|
||||
GL_NOR, // Nor
|
||||
GL_XOR, // Xor
|
||||
GL_EQUIV, // Equiv
|
||||
GL_AND_INVERTED, // AndInverted
|
||||
GL_OR_REVERSE, // OrReverse
|
||||
GL_OR_INVERTED, // OrInverted
|
||||
};
|
||||
|
||||
// Range check table for input
|
||||
if ((unsigned)op >= ARRAY_SIZE(logic_op_table)) {
|
||||
LOG_CRITICAL(Render_OpenGL, "Unknown logic op %d", op);
|
||||
UNREACHABLE();
|
||||
|
||||
return GL_COPY;
|
||||
}
|
||||
|
||||
return logic_op_table[(unsigned)op];
|
||||
}
|
||||
|
||||
inline GLenum CompareFunc(Pica::Regs::CompareFunc func) {
|
||||
static const GLenum compare_func_table[] = {
|
||||
GL_NEVER, // CompareFunc::Never
|
||||
|
||||
@ -119,17 +119,13 @@ static void ProcessShaderCode(VertexShaderState& state) {
|
||||
switch (instr.opcode.Value().GetInfo().type) {
|
||||
case OpCode::Type::Arithmetic:
|
||||
{
|
||||
bool is_inverted = 0 != (instr.opcode.Value().GetInfo().subtype & OpCode::Info::SrcInversed);
|
||||
// TODO: We don't really support this properly: For instance, the address register
|
||||
// offset needs to be applied to SRC2 instead, etc.
|
||||
// For now, we just abort in this situation.
|
||||
ASSERT_MSG(!is_inverted, "Bad condition...");
|
||||
const bool is_inverted = (0 != (instr.opcode.Value().GetInfo().subtype & OpCode::Info::SrcInversed));
|
||||
|
||||
const int address_offset = (instr.common.address_register_index == 0)
|
||||
? 0 : state.address_registers[instr.common.address_register_index - 1];
|
||||
|
||||
const float24* src1_ = LookupSourceRegister(instr.common.GetSrc1(is_inverted) + address_offset);
|
||||
const float24* src2_ = LookupSourceRegister(instr.common.GetSrc2(is_inverted));
|
||||
const float24* src1_ = LookupSourceRegister(instr.common.GetSrc1(is_inverted) + (!is_inverted * address_offset));
|
||||
const float24* src2_ = LookupSourceRegister(instr.common.GetSrc2(is_inverted) + ( is_inverted * address_offset));
|
||||
|
||||
const bool negate_src1 = ((bool)swizzle.negate_src1 != false);
|
||||
const bool negate_src2 = ((bool)swizzle.negate_src2 != false);
|
||||
@ -208,6 +204,15 @@ static void ProcessShaderCode(VertexShaderState& state) {
|
||||
}
|
||||
break;
|
||||
|
||||
case OpCode::Id::MIN:
|
||||
for (int i = 0; i < 4; ++i) {
|
||||
if (!swizzle.DestComponentEnabled(i))
|
||||
continue;
|
||||
|
||||
dest[i] = std::min(src1[i], src2[i]);
|
||||
}
|
||||
break;
|
||||
|
||||
case OpCode::Id::DP3:
|
||||
case OpCode::Id::DP4:
|
||||
{
|
||||
@ -279,6 +284,16 @@ static void ProcessShaderCode(VertexShaderState& state) {
|
||||
break;
|
||||
}
|
||||
|
||||
case OpCode::Id::SLT:
|
||||
case OpCode::Id::SLTI:
|
||||
for (int i = 0; i < 4; ++i) {
|
||||
if (!swizzle.DestComponentEnabled(i))
|
||||
continue;
|
||||
|
||||
dest[i] = (src1[i] < src2[i]) ? float24::FromFloat32(1.0f) : float24::FromFloat32(0.0f);
|
||||
}
|
||||
break;
|
||||
|
||||
case OpCode::Id::CMP:
|
||||
for (int i = 0; i < 2; ++i) {
|
||||
// TODO: Can you restrict to one compare via dest masking?
|
||||
|
||||
Loading…
Reference in New Issue
Block a user