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gcc 11 compatibility fix (suggestion) (#5778)

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Fixes missing include and runtime variable in offsetof

* gcc 11 compatibility fix

* Revert "gcc 11 compatibility fix"

This reverts commit bf5711d944bbdf7b5663ba4fec1b9066f16e2bb2.

* gcc 11 compatibility fix (with pointer math)

* Don't require pointers for framebuffer field math

* Code style fix (clang-format)
This commit is contained in:
Max Fedotov 2021-05-11 06:10:29 +03:00 committed by GitHub
parent 6e16081b6a
commit a2f34ea82b
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GPG Key ID: 4AEE18F83AFDEB23
3 changed files with 23 additions and 14 deletions
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1
src/common/ring_buffer.h
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@ -9,6 +9,7 @@
#include <atomic> #include <atomic>
#include <cstddef> #include <cstddef>
#include <cstring> #include <cstring>
#include <limits>
#include <new> #include <new>
#include <type_traits> #include <type_traits>
#include <vector> #include <vector>

26
src/core/hle/service/gsp/gsp_gpu.cpp
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@ -283,28 +283,28 @@ ResultCode SetBufferSwap(u32 screen_id, const FrameBufferInfo& info) {
PAddr phys_address_left = VirtualToPhysicalAddress(info.address_left); PAddr phys_address_left = VirtualToPhysicalAddress(info.address_left);
PAddr phys_address_right = VirtualToPhysicalAddress(info.address_right); PAddr phys_address_right = VirtualToPhysicalAddress(info.address_right);
if (info.active_fb == 0) { if (info.active_fb == 0) {
WriteSingleHWReg(base_address + 4 * static_cast<u32>(GPU_REG_INDEX( WriteSingleHWReg(base_address + 4 * static_cast<u32>(GPU_FRAMEBUFFER_REG_INDEX(
framebuffer_config[screen_id].address_left1)), screen_id, address_left1)),
phys_address_left); phys_address_left);
WriteSingleHWReg(base_address + 4 * static_cast<u32>(GPU_REG_INDEX( WriteSingleHWReg(base_address + 4 * static_cast<u32>(GPU_FRAMEBUFFER_REG_INDEX(
framebuffer_config[screen_id].address_right1)), screen_id, address_right1)),
phys_address_right); phys_address_right);
} else { } else {
WriteSingleHWReg(base_address + 4 * static_cast<u32>(GPU_REG_INDEX( WriteSingleHWReg(base_address + 4 * static_cast<u32>(GPU_FRAMEBUFFER_REG_INDEX(
framebuffer_config[screen_id].address_left2)), screen_id, address_left2)),
phys_address_left); phys_address_left);
WriteSingleHWReg(base_address + 4 * static_cast<u32>(GPU_REG_INDEX( WriteSingleHWReg(base_address + 4 * static_cast<u32>(GPU_FRAMEBUFFER_REG_INDEX(
framebuffer_config[screen_id].address_right2)), screen_id, address_right2)),
phys_address_right); phys_address_right);
} }
WriteSingleHWReg(base_address + WriteSingleHWReg(base_address +
4 * static_cast<u32>(GPU_REG_INDEX(framebuffer_config[screen_id].stride)), 4 * static_cast<u32>(GPU_FRAMEBUFFER_REG_INDEX(screen_id, stride)),
info.stride); info.stride);
WriteSingleHWReg(base_address + 4 * static_cast<u32>(GPU_REG_INDEX( WriteSingleHWReg(base_address +
framebuffer_config[screen_id].color_format)), 4 * static_cast<u32>(GPU_FRAMEBUFFER_REG_INDEX(screen_id, color_format)),
info.format); info.format);
WriteSingleHWReg( WriteSingleHWReg(base_address +
base_address + 4 * static_cast<u32>(GPU_REG_INDEX(framebuffer_config[screen_id].active_fb)), 4 * static_cast<u32>(GPU_FRAMEBUFFER_REG_INDEX(screen_id, active_fb)),
info.shown_fb); info.shown_fb);
if (Pica::g_debug_context) if (Pica::g_debug_context)

8
src/core/hw/gpu.h
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@ -30,6 +30,14 @@ constexpr double SCREEN_REFRESH_RATE = BASE_CLOCK_RATE_ARM11 / static_cast<doubl
// Returns index corresponding to the Regs member labeled by field_name // Returns index corresponding to the Regs member labeled by field_name
#define GPU_REG_INDEX(field_name) (offsetof(GPU::Regs, field_name) / sizeof(u32)) #define GPU_REG_INDEX(field_name) (offsetof(GPU::Regs, field_name) / sizeof(u32))
// Returns index corresponding to the Regs::FramebufferConfig labeled by field_name
// screen_id is a subscript for Regs::framebuffer_config
#define GPU_FRAMEBUFFER_REG_INDEX(screen_id, field_name) \
((offsetof(GPU::Regs, framebuffer_config) + \
sizeof(GPU::Regs::FramebufferConfig) * (screen_id) + \
offsetof(GPU::Regs::FramebufferConfig, field_name)) / \
sizeof(u32))
// MMIO region 0x1EFxxxxx // MMIO region 0x1EFxxxxx
struct Regs { struct Regs {