midou/citra
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Kernel/Threads: Don't clear the CPU instruction cache when performing a context switch from an idle thread into a thread in the same process.

Browse Source 
We were unnecessarily clearing the cache when going from Process A -> Idle -> Process A, this caused extreme performance regressions.
This commit is contained in:
Subv 2017-07-22 19:37:26 -05:00
parent 214150f00c
commit b178089251
1 changed files with 3 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/core/hle/kernel/thread.cpp
View File

@ -171,6 +171,8 @@ static void SwitchContext(Thread* new_thread) {
// Cancel any outstanding wakeup events for this thread // Cancel any outstanding wakeup events for this thread
CoreTiming::UnscheduleEvent(ThreadWakeupEventType, new_thread->callback_handle); CoreTiming::UnscheduleEvent(ThreadWakeupEventType, new_thread->callback_handle);
auto previous_process = Kernel::g_current_process;
current_thread = new_thread; current_thread = new_thread;
ready_queue.remove(new_thread->current_priority, new_thread); ready_queue.remove(new_thread->current_priority, new_thread);
@ -179,7 +181,7 @@ static void SwitchContext(Thread* new_thread) {
Core::CPU().LoadContext(new_thread->context); Core::CPU().LoadContext(new_thread->context);
Core::CPU().SetCP15Register(CP15_THREAD_URO, new_thread->GetTLSAddress()); Core::CPU().SetCP15Register(CP15_THREAD_URO, new_thread->GetTLSAddress());
if (!previous_thread || previous_thread->owner_process != current_thread->owner_process) { if (previous_process != current_thread->owner_process) {
Kernel::g_current_process = current_thread->owner_process; Kernel::g_current_process = current_thread->owner_process;
Memory::current_page_table = &Kernel::g_current_process->vm_manager.page_table; Memory::current_page_table = &Kernel::g_current_process->vm_manager.page_table;
// We have switched processes and thus, page tables, clear the instruction cache so we // We have switched processes and thus, page tables, clear the instruction cache so we