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Merge pull request #1618 from 86Box/master

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Bring the branch up to par with master.
This commit is contained in:
Miran Grča
2021-08-20 16:58:49 +02:00
committed by GitHub
parent 19c374c046 8d3a7583de
commit a0d855823a
6 changed files with 746 additions and 321 deletions
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2
README.md
View File

@@ -46,7 +46,7 @@ Community
---------
We operate an IRC channel and a Discord server for discussing 86Box, its development and anything related to retro computing. We look forward to hearing from you!
[![Visit our IRC channel](https://kiwiirc.com/buttons/irc.ringoflightning.net/softhistory.png)](https://kiwiirc.com/client/irc.ringoflightning.net/?nick=86box|?#softhistory)
[![Visit our IRC channel](https://kiwiirc.com/buttons/irc.ringoflightning.net/86Box.png)](https://kiwiirc.com/client/irc.ringoflightning.net/?nick=86box|?#86Box)
[![Visit our Discord server](https://discordapp.com/api/guilds/262614059009048590/embed.png)](https://discord.gg/QXK9XTv)

1
src/include/86box/scsi_ncr5380.h
View File

@@ -26,6 +26,7 @@
extern const device_t scsi_lcs6821n_device;
extern const device_t scsi_rt1000b_device;
extern const device_t scsi_t128_device;
extern const device_t scsi_t130b_device;
#if defined(DEV_BRANCH) && defined(USE_SUMO)
extern const device_t scsi_scsiat_device;

1
src/scsi/scsi.c
View File

@@ -69,6 +69,7 @@ static SCSI_CARD scsi_cards[] = {
{ "bt545s", &buslogic_545s_device, },
{ "lcs6821n", &scsi_lcs6821n_device, },
{ "rt1000b", &scsi_rt1000b_device, },
{ "t128", &scsi_t128_device, },
{ "t130b", &scsi_t130b_device, },
#ifdef WALTJE
{ "scsiat", &scsi_scsiat_device, },

575
src/scsi/scsi_ncr5380.c
View File

@@ -47,6 +47,7 @@
#define RT1000B_810R_ROM "roms/scsi/ncr5380/Rancho_RT1000_RTBios_version_8.10R.bin"
#define RT1000B_820R_ROM "roms/scsi/ncr5380/RTBIOS82.rom"
#define T130B_ROM "roms/scsi/ncr5380/trantor_t130b_bios_v2.14.bin"
#define T128_ROM "roms/scsi/ncr5380/trantor_t128_bios_v1.12.bin"
#define NCR_CURDATA 0 /* current SCSI data (read only) */
@@ -108,8 +109,22 @@ typedef struct {
int command_pos, data_pos;
} ncr_t;
typedef struct {
uint8_t ctrl;
uint8_t status;
uint8_t buffer[512];
uint8_t ext_ram[0x80];
uint8_t block_count;
int block_loaded;
int pos, host_pos;
int bios_enabled, int_lock;
} t128_t;
typedef struct {
ncr_t ncr;
t128_t t128;
const char *name;
@@ -122,7 +137,7 @@ typedef struct {
int8_t irq;
int8_t type;
int8_t bios_ver;
uint8_t block_count, block_count_num;
uint8_t block_count;
uint8_t status_ctrl;
uint8_t bus, pad;
@@ -247,15 +262,19 @@ ncr_timer_on(ncr5380_t *ncr_dev, ncr_t *ncr, int callback)
double p = ncr_dev->period;
if (ncr->data_wait & 2)
ncr->data_wait &= ~2;
ncr->data_wait &= ~2;
if (callback) {
if (ncr_dev->type == 3)
p *= 512.0;
else
p *= 128.0;
}
if (callback)
p *= 128.0;
p += 1.0;
ncr_log("P = %lf\n", p);
timer_on_auto(&ncr_dev->timer, p);
p += 1.0;
ncr_log("P = %lf, command = %02x, callback = %i, period = %lf, t128 pos = %i\n", p, ncr->command[0], callback, ncr_dev->period, ncr_dev->t128.host_pos);
timer_on_auto(&ncr_dev->timer, p);
}
@@ -451,8 +470,9 @@ ncr_bus_update(void *priv, int bus)
p = scsi_device_get_callback(dev);
if (p <= 0.0) {
ncr_dev->period = 0.2;
} else
} else {
ncr_dev->period = p / ((double) dev->buffer_length);
}
ncr->data_wait |= 2;
ncr_log("SCSI ID %i: command 0x%02x for p = %lf, update = %lf, len = %i\n", ncr->target_id, ncr->command[0], p, ncr_dev->period, dev->buffer_length);
}
@@ -563,13 +583,14 @@ ncr_write(uint16_t port, uint8_t val, void *priv)
{
ncr5380_t *ncr_dev = (ncr5380_t *)priv;
ncr_t *ncr = &ncr_dev->ncr;
scsi_device_t *dev = &scsi_devices[ncr_dev->bus][ncr->target_id];
int bus_host = 0;
ncr_log("NCR5380 write(%04x,%02x)\n",port & 7,val);
ncr_log("NCR5380 write(%04x,%02x)\n",port & 7,val);
switch (port & 7) {
case 0: /* Output data register */
ncr_log("Write: Output data register\n");
ncr_log("Write: Output data register, val = %02x\n", val);
ncr->output_data = val;
break;
@@ -591,18 +612,34 @@ ncr_write(uint16_t port, uint8_t val, void *priv)
ncr->mode = val;
/*Don't stop the timer until it finishes the transfer*/
if (ncr_dev->block_count_loaded && (ncr->mode & MODE_DMA) && !timer_is_enabled(&ncr_dev->timer)) {
ncr_log("Continuing DMA mode\n");
ncr_timer_on(ncr_dev, ncr, 0);
}
if (ncr_dev->type == 3) {
/*Don't stop the timer until it finishes the transfer*/
if (ncr_dev->t128.block_loaded && (ncr->mode & MODE_DMA)) {
ncr_log("Continuing DMA mode\n");
ncr_timer_on(ncr_dev, ncr, 0);
}
/*When a pseudo-DMA transfer has completed (Send or Initiator Receive), mark it as complete and idle the status*/
if (!ncr_dev->t128.block_loaded && !(ncr->mode & MODE_DMA)) {
ncr_log("No DMA mode\n");
ncr->tcr &= ~TCR_LAST_BYTE_SENT;
ncr->isr &= ~STATUS_END_OF_DMA;
ncr->dma_mode = DMA_IDLE;
}
} else {
/*Don't stop the timer until it finishes the transfer*/
if (ncr_dev->block_count_loaded && (ncr->mode & MODE_DMA) && !timer_is_enabled(&ncr_dev->timer)) {
ncr_log("Continuing DMA mode\n");
ncr_timer_on(ncr_dev, ncr, 0);
}
/*When a pseudo-DMA transfer has completed (Send or Initiator Receive), mark it as complete and idle the status*/
if (!ncr_dev->block_count_loaded && !(ncr->mode & MODE_DMA)) {
ncr_log("No DMA mode\n");
ncr->tcr &= ~TCR_LAST_BYTE_SENT;
ncr->isr &= ~STATUS_END_OF_DMA;
ncr->dma_mode = DMA_IDLE;
/*When a pseudo-DMA transfer has completed (Send or Initiator Receive), mark it as complete and idle the status*/
if (!ncr_dev->block_count_loaded && !(ncr->mode & MODE_DMA)) {
ncr_log("No DMA mode\n");
ncr->tcr &= ~TCR_LAST_BYTE_SENT;
ncr->isr &= ~STATUS_END_OF_DMA;
ncr->dma_mode = DMA_IDLE;
}
}
break;
@@ -619,8 +656,18 @@ ncr_write(uint16_t port, uint8_t val, void *priv)
ncr_log("Write: start DMA send register\n");
/*a Write 6/10 has occurred, start the timer when the block count is loaded*/
ncr->dma_mode = DMA_SEND;
if ((ncr->mode & MODE_DMA) && !timer_is_enabled(&ncr_dev->timer)) {
ncr_timer_on(ncr_dev, ncr, 0);
if (ncr_dev->type == 3) {
ncr_log("DMA send timer start, enabled? = %i\n", timer_is_enabled(&ncr_dev->timer));
ncr_dev->t128.block_count = dev->buffer_length >> 9;
ncr_dev->t128.block_loaded = 1;
ncr_dev->t128.host_pos = 0;
ncr_dev->t128.status |= 0x04;
} else {
if ((ncr->mode & MODE_DMA) && !timer_is_enabled(&ncr_dev->timer)) {
ncr_log("DMA send timer on\n");
ncr_timer_on(ncr_dev, ncr, 0);
}
}
break;
@@ -628,8 +675,19 @@ ncr_write(uint16_t port, uint8_t val, void *priv)
ncr_log("Write: start DMA initiator receive register, dma? = %02x\n", ncr->mode & MODE_DMA);
/*a Read 6/10 has occurred, start the timer when the block count is loaded*/
ncr->dma_mode = DMA_INITIATOR_RECEIVE;
if ((ncr->mode & MODE_DMA) && !timer_is_enabled(&ncr_dev->timer)) {
ncr_timer_on(ncr_dev, ncr, 0);
if (ncr_dev->type == 3) {
ncr_log("DMA receive timer start, enabled? = %i\n", timer_is_enabled(&ncr_dev->timer));
ncr_dev->t128.block_count = dev->buffer_length >> 9;
ncr_dev->t128.block_loaded = 1;
ncr_dev->t128.host_pos = 512;
ncr_dev->t128.status |= 0x04;
timer_on_auto(&ncr_dev->timer, 0.2);
} else {
if ((ncr->mode & MODE_DMA) && !timer_is_enabled(&ncr_dev->timer)) {
ncr_log("DMA receive timer start\n");
ncr_timer_on(ncr_dev, ncr, 0);
}
}
break;
@@ -637,8 +695,8 @@ ncr_write(uint16_t port, uint8_t val, void *priv)
ncr_log("NCR5380: bad write %04x %02x\n", port, val);
break;
}
if (ncr->dma_mode == DMA_IDLE || ncr_dev->type == 0) {
if (ncr->dma_mode == DMA_IDLE || ncr_dev->type == 0 || ncr_dev->type == 3) {
bus_host = get_bus_host(ncr);
ncr_bus_update(priv, bus_host);
}
@@ -658,7 +716,7 @@ ncr_read(uint16_t port, void *priv)
ncr_log("Read: Current SCSI data register\n");
if (ncr->icr & ICR_DBP) {
/*Return the data from the output register if on data bus phase from ICR*/
ncr_log("Data Bus Phase\n");
ncr_log("Data Bus Phase, ret = %02x\n", ncr->output_data);
ret = ncr->output_data;
} else {
/*Return the data from the SCSI bus*/
@@ -792,11 +850,10 @@ memio_read(uint32_t addr, void *priv)
ret = 0xff;
} else {
ret = ncr_dev->buffer[ncr_dev->buffer_host_pos++];
ncr_log("Read Host pos = %i\n", ncr_dev->buffer_host_pos);
if (ncr_dev->buffer_host_pos == 128) {
ncr_log("Not ready\n");
ncr_dev->status_ctrl |= STATUS_BUFFER_NOT_READY;
ncr_log("Transfer busy read, status = %02x\n", ncr_dev->status_ctrl);
}
}
break;
@@ -860,7 +917,7 @@ memio_write(uint32_t addr, uint8_t val, void *priv)
if (!(ncr_dev->status_ctrl & CTRL_DATA_DIR) && ncr_dev->buffer_host_pos < 128) {
ncr_dev->buffer[ncr_dev->buffer_host_pos++] = val;
ncr_log("Write host pos = %i\n", ncr_dev->buffer_host_pos);
ncr_log("Write host pos = %i, val = %02x\n", ncr_dev->buffer_host_pos, val);
if (ncr_dev->buffer_host_pos == 128) {
ncr_dev->status_ctrl |= STATUS_BUFFER_NOT_READY;
@@ -991,7 +1048,7 @@ ncr_dma_send(ncr5380_t *ncr_dev, ncr_t *ncr, scsi_device_t *dev)
int bus, c = 0;
uint8_t data;
if (scsi_device_get_callback(dev) > 0.0)
if (scsi_device_get_callback(dev) > 0.0)
ncr_timer_on(ncr_dev, ncr, 1);
else
ncr_timer_on(ncr_dev, ncr, 0);
@@ -1003,37 +1060,65 @@ ncr_dma_send(ncr5380_t *ncr_dev, ncr_t *ncr, scsi_device_t *dev)
}
/* Data ready. */
data = ncr_dev->buffer[ncr_dev->buffer_pos];
if (ncr_dev->type == 3) {
data = ncr_dev->t128.buffer[ncr_dev->t128.pos];
} else
data = ncr_dev->buffer[ncr_dev->buffer_pos];
bus = get_bus_host(ncr) & ~BUS_DATAMASK;
bus |= BUS_SETDATA(data);
ncr_bus_update(ncr_dev, bus | BUS_ACK);
ncr_bus_update(ncr_dev, bus & ~BUS_ACK);
ncr_dev->buffer_pos++;
ncr_log("Buffer pos for writing = %d\n", ncr_dev->buffer_pos);
if (ncr_dev->type == 3) {
ncr_dev->t128.pos++;
ncr_log("Buffer pos for writing = %d, data = %02x\n", ncr_dev->t128.pos, data);
if (ncr_dev->buffer_pos == 128) {
ncr_dev->buffer_pos = 0;
ncr_dev->buffer_host_pos = 0;
ncr_dev->status_ctrl &= ~STATUS_BUFFER_NOT_READY;
ncr_dev->ncr_busy = 0;
ncr_dev->block_count = (ncr_dev->block_count - 1) & 0xff;
ncr_log("Remaining blocks to be written=%d\n", ncr_dev->block_count);
if (!ncr_dev->block_count) {
ncr_dev->block_count_loaded = 0;
ncr_log("IO End of write transfer\n");
ncr->tcr |= TCR_LAST_BYTE_SENT;
ncr->isr |= STATUS_END_OF_DMA;
timer_stop(&ncr_dev->timer);
if (ncr->mode & MODE_ENA_EOP_INT) {
ncr_log("NCR write irq\n");
ncr_irq(ncr_dev, ncr, 1);
}
if (ncr_dev->t128.pos == 512) {
ncr_dev->t128.pos = 0;
ncr_dev->t128.host_pos = 0;
ncr_dev->t128.status &= ~0x02;
ncr_dev->t128.block_count = (ncr_dev->t128.block_count - 1) & 0xff;
ncr_log("Remaining blocks to be written=%d\n", ncr_dev->t128.block_count);
if (!ncr_dev->t128.block_count) {
ncr_dev->t128.block_loaded = 0;
ncr_log("IO End of write transfer\n");
ncr->tcr |= TCR_LAST_BYTE_SENT;
ncr->isr |= STATUS_END_OF_DMA;
timer_stop(&ncr_dev->timer);
if (ncr->mode & MODE_ENA_EOP_INT) {
ncr_log("NCR write irq\n");
ncr_irq(ncr_dev, ncr, 1);
}
}
return;
}
} else {
ncr_dev->buffer_pos++;
ncr_log("Buffer pos for writing = %d\n", ncr_dev->buffer_pos);
if (ncr_dev->buffer_pos == 128) {
ncr_dev->buffer_pos = 0;
ncr_dev->buffer_host_pos = 0;
ncr_dev->status_ctrl &= ~STATUS_BUFFER_NOT_READY;
ncr_dev->ncr_busy = 0;
ncr_dev->block_count = (ncr_dev->block_count - 1) & 0xff;
ncr_log("Remaining blocks to be written=%d\n", ncr_dev->block_count);
if (!ncr_dev->block_count) {
ncr_dev->block_count_loaded = 0;
ncr_log("IO End of write transfer\n");
ncr->tcr |= TCR_LAST_BYTE_SENT;
ncr->isr |= STATUS_END_OF_DMA;
timer_stop(&ncr_dev->timer);
if (ncr->mode & MODE_ENA_EOP_INT) {
ncr_log("NCR write irq\n");
ncr_irq(ncr_dev, ncr, 1);
}
}
return;
}
}
return;
}
ncr_dma_send(ncr_dev, ncr, dev);
ncr_dma_send(ncr_dev, ncr, dev);
}
static void
@@ -1041,12 +1126,13 @@ ncr_dma_initiator_receive(ncr5380_t *ncr_dev, ncr_t *ncr, scsi_device_t *dev)
{
int bus, c = 0;
uint8_t temp;
if (scsi_device_get_callback(dev) > 0.0)
ncr_timer_on(ncr_dev, ncr, 1);
else
ncr_timer_on(ncr_dev, ncr, 0);
if (scsi_device_get_callback(dev) > 0.0) {
ncr_timer_on(ncr_dev, ncr, 1);
} else {
ncr_timer_on(ncr_dev, ncr, 0);
}
for (c = 0; c < 10; c++) {
ncr_bus_read(ncr_dev);
if (ncr->cur_bus & BUS_REQ)
@@ -1061,28 +1147,52 @@ ncr_dma_initiator_receive(ncr5380_t *ncr_dev, ncr_t *ncr, scsi_device_t *dev)
ncr_bus_update(ncr_dev, bus | BUS_ACK);
ncr_bus_update(ncr_dev, bus & ~BUS_ACK);
ncr_dev->buffer[ncr_dev->buffer_pos++] = temp;
ncr_log("Buffer pos for reading = %d\n", ncr_dev->buffer_pos);
if (ncr_dev->buffer_pos == 128) {
ncr_dev->buffer_pos = 0;
ncr_dev->buffer_host_pos = 0;
ncr_dev->status_ctrl &= ~STATUS_BUFFER_NOT_READY;
ncr_dev->block_count = (ncr_dev->block_count - 1) & 0xff;
ncr_log("Remaining blocks to be read=%d\n", ncr_dev->block_count);
if (!ncr_dev->block_count) {
ncr_dev->block_count_loaded = 0;
ncr_log("IO End of read transfer\n");
ncr->isr |= STATUS_END_OF_DMA;
timer_stop(&ncr_dev->timer);
if (ncr->mode & MODE_ENA_EOP_INT) {
ncr_log("NCR read irq\n");
ncr_irq(ncr_dev, ncr, 1);
}
}
return;
}
if (ncr_dev->type == 3) {
ncr_dev->t128.buffer[ncr_dev->t128.pos++] = temp;
ncr_log("Buffer pos for reading = %d, temp = %02x\n", ncr_dev->t128.pos, temp);
if (ncr_dev->t128.pos == 512) {
ncr_dev->t128.pos = 0;
ncr_dev->t128.host_pos = 0;
ncr_dev->t128.status &= ~0x02;
ncr_dev->t128.block_count = (ncr_dev->t128.block_count - 1) & 0xff;
ncr_log("Remaining blocks to be read=%d, status=%02x, len=%i\n", ncr_dev->t128.block_count, ncr_dev->t128.status, dev->buffer_length);
if (!ncr_dev->t128.block_count) {
ncr_dev->t128.block_loaded = 0;
ncr_log("IO End of read transfer\n");
ncr->isr |= STATUS_END_OF_DMA;
timer_stop(&ncr_dev->timer);
if (ncr->mode & MODE_ENA_EOP_INT) {
ncr_log("NCR read irq\n");
ncr_irq(ncr_dev, ncr, 1);
}
}
return;
}
} else {
ncr_dev->buffer[ncr_dev->buffer_pos++] = temp;
ncr_log("Buffer pos for reading = %d\n", ncr_dev->buffer_pos);
if (ncr_dev->buffer_pos == 128) {
ncr_dev->buffer_pos = 0;
ncr_dev->buffer_host_pos = 0;
ncr_dev->status_ctrl &= ~STATUS_BUFFER_NOT_READY;
ncr_dev->block_count = (ncr_dev->block_count - 1) & 0xff;
ncr_log("Remaining blocks to be read=%d\n", ncr_dev->block_count);
if (!ncr_dev->block_count) {
ncr_dev->block_count_loaded = 0;
ncr_log("IO End of read transfer\n");
ncr->isr |= STATUS_END_OF_DMA;
timer_stop(&ncr_dev->timer);
if (ncr->mode & MODE_ENA_EOP_INT) {
ncr_log("NCR read irq\n");
ncr_irq(ncr_dev, ncr, 1);
}
}
return;
}
}
ncr_dma_initiator_receive(ncr_dev, ncr, dev);
}
@@ -1093,11 +1203,21 @@ ncr_callback(void *priv)
ncr_t *ncr = &ncr_dev->ncr;
scsi_device_t *dev = &scsi_devices[ncr_dev->bus][ncr->target_id];
ncr_log("DMA mode=%d, status ctrl = %02x\n", ncr->dma_mode, ncr_dev->status_ctrl);
if (ncr->dma_mode != DMA_IDLE && (ncr->mode & MODE_DMA) && ncr_dev->block_count_loaded) {
ncr_timer_on(ncr_dev, ncr, 0);
}
if (ncr_dev->type == 3) {
ncr_log("DMA Callback, load = %i\n", ncr_dev->t128.block_loaded);
if (ncr->dma_mode != DMA_IDLE && (ncr->mode & MODE_DMA) && ncr_dev->t128.block_loaded) {
ncr_log("Timer on! Host POS = %i, status = %02x, DMA mode = %i, Period = %lf\n", ncr_dev->t128.host_pos, ncr_dev->t128.status, ncr->dma_mode, scsi_device_get_callback(dev));
if (ncr_dev->t128.host_pos == 512 && ncr_dev->t128.block_count) {
ncr_dev->t128.status |= 0x04;
ncr_timer_on(ncr_dev, ncr, 0);
}
}
} else {
ncr_log("DMA mode=%d, status ctrl = %02x\n", ncr->dma_mode, ncr_dev->status_ctrl);
if (ncr->dma_mode != DMA_IDLE && (ncr->mode & MODE_DMA) && ncr_dev->block_count_loaded) {
ncr_timer_on(ncr_dev, ncr, 0);
}
}
if (ncr->data_wait & 1) {
ncr->clear_req = 3;
@@ -1109,36 +1229,64 @@ ncr_callback(void *priv)
switch(ncr->dma_mode) {
case DMA_SEND:
if (ncr_dev->status_ctrl & CTRL_DATA_DIR) {
ncr_log("DMA_SEND with DMA direction set wrong\n");
break;
}
if (!(ncr_dev->status_ctrl & STATUS_BUFFER_NOT_READY)) {
ncr_log("Write buffer status ready\n");
break;
}
if (ncr_dev->type != 3) {
if (ncr_dev->status_ctrl & CTRL_DATA_DIR) {
ncr_log("DMA_SEND with DMA direction set wrong\n");
break;
}
if (!(ncr_dev->status_ctrl & STATUS_BUFFER_NOT_READY)) {
ncr_log("Write buffer status ready\n");
break;
}
if (!ncr_dev->block_count_loaded)
break;
if (!ncr_dev->block_count_loaded)
break;
} else {
if (!(ncr_dev->t128.status & 0x04)) {
ncr_log("Write status busy\n");
break;
}
if (!ncr_dev->t128.block_loaded) {
ncr_log("Write block not loaded\n");
break;
}
if (ncr_dev->t128.host_pos < 512)
break;
}
ncr_dma_send(ncr_dev, ncr, dev);
break;
case DMA_INITIATOR_RECEIVE:
if (!(ncr_dev->status_ctrl & CTRL_DATA_DIR)) {
ncr_log("DMA_INITIATOR_RECEIVE with DMA direction set wrong\n");
break;
if (ncr_dev->type != 3) {
if (!(ncr_dev->status_ctrl & CTRL_DATA_DIR)) {
ncr_log("DMA_INITIATOR_RECEIVE with DMA direction set wrong\n");
break;
}
if (!(ncr_dev->status_ctrl & STATUS_BUFFER_NOT_READY)) {
ncr_log("Read buffer status ready\n");
break;
}
if (!ncr_dev->block_count_loaded)
break;
} else {
if (!(ncr_dev->t128.status & 0x04)) {
ncr_log("Read status busy, block count = %i, host pos = %i\n", ncr_dev->t128.block_count, ncr_dev->t128.host_pos);
break;
}
if (!ncr_dev->t128.block_loaded) {
ncr_log("Read block not loaded\n");
break;
}
if (ncr_dev->t128.host_pos < 512)
break;
}
if (!(ncr_dev->status_ctrl & STATUS_BUFFER_NOT_READY)) {
ncr_log("Read buffer status ready\n");
break;
}
if (!ncr_dev->block_count_loaded)
break;
ncr_dma_initiator_receive(ncr_dev, ncr, dev);
break;
}
@@ -1153,6 +1301,109 @@ ncr_callback(void *priv)
}
}
static uint8_t
t128_read(uint32_t addr, void *priv)
{
ncr5380_t *ncr_dev = (ncr5380_t *)priv;
ncr_t *ncr = &ncr_dev->ncr;
uint8_t ret = 0xff;
addr &= 0x3fff;
if (addr >= 0 && addr < 0x1800)
ret = ncr_dev->bios_rom.rom[addr & 0x1fff];
else if (addr >= 0x1800 && addr < 0x1880)
ret = ncr_dev->t128.ext_ram[addr & 0x7f];
else if (addr >= 0x1c00 && addr < 0x1c20) {
ret = ncr_dev->t128.ctrl;
} else if (addr >= 0x1c20 && addr < 0x1c40) {
ret = ncr_dev->t128.status;
ncr_log("T128 status read = %02x, cur bus = %02x, req = %02x, dma = %02x\n", ret, ncr->cur_bus, ncr->cur_bus & BUS_REQ, ncr->mode & MODE_DMA);
} else if (addr >= 0x1d00 && addr < 0x1e00) {
if (addr >= 0x1d00 && addr < 0x1d20)
ret = ncr_read(0, ncr_dev);
else if (addr >= 0x1d20 && addr < 0x1d40)
ret = ncr_read(1, ncr_dev);
else if (addr >= 0x1d40 && addr < 0x1d60)
ret = ncr_read(2, ncr_dev);
else if (addr >= 0x1d60 && addr < 0x1d80)
ret = ncr_read(3, ncr_dev);
else if (addr >= 0x1d80 && addr < 0x1da0)
ret = ncr_read(4, ncr_dev);
else if (addr >= 0x1da0 && addr < 0x1dc0)
ret = ncr_read(5, ncr_dev);
else if (addr >= 0x1dc0 && addr < 0x1de0)
ret = ncr_read(6, ncr_dev);
else if (addr >= 0x1de0 && addr < 0x1e00)
ret = ncr_read(7, ncr_dev);
} else if (addr >= 0x1e00 && addr < 0x2000) {
if (ncr_dev->t128.host_pos >= 512 || ncr->dma_mode != DMA_INITIATOR_RECEIVE) {
ret = 0xff;
} else {
ret = ncr_dev->t128.buffer[ncr_dev->t128.host_pos++];
ncr_log("Read transfer, addr = %i, pos = %i\n", addr & 0x1ff, ncr_dev->t128.host_pos);
if (ncr_dev->t128.host_pos == 512) {
ncr_dev->t128.status &= ~0x04;
ncr_log("Transfer busy read, status = %02x, period = %lf\n", ncr_dev->t128.status, ncr_dev->period);
if (ncr_dev->period == 0.2)
timer_on_auto(&ncr_dev->timer, 40.2);
}
}
}
return(ret);
}
static void
t128_write(uint32_t addr, uint8_t val, void *priv)
{
ncr5380_t *ncr_dev = (ncr5380_t *)priv;
ncr_t *ncr = &ncr_dev->ncr;
addr &= 0x3fff;
if (addr >= 0x1800 && addr < 0x1880)
ncr_dev->t128.ext_ram[addr & 0x7f] = val;
else if (addr >= 0x1c00 && addr < 0x1c20) {
if ((val & 0x02) && !(ncr_dev->t128.ctrl & 0x02)) {
ncr_dev->t128.status |= 0x02;
ncr_log("Timer fired\n");
}
ncr_dev->t128.ctrl = val;
ncr_log("T128 ctrl write = %02x\n", val);
} else if (addr >= 0x1d00 && addr < 0x1e00) {
if (addr >= 0x1d00 && addr < 0x1d20)
ncr_write(0, val, ncr_dev);
else if (addr >= 0x1d20 && addr < 0x1d40)
ncr_write(1, val, ncr_dev);
else if (addr >= 0x1d40 && addr < 0x1d60)
ncr_write(2, val, ncr_dev);
else if (addr >= 0x1d60 && addr < 0x1d80)
ncr_write(3, val, ncr_dev);
else if (addr >= 0x1d80 && addr < 0x1da0)
ncr_write(4, val, ncr_dev);
else if (addr >= 0x1da0 && addr < 0x1dc0)
ncr_write(5, val, ncr_dev);
else if (addr >= 0x1dc0 && addr < 0x1de0)
ncr_write(6, val, ncr_dev);
else if (addr >= 0x1de0 && addr < 0x1e00)
ncr_write(7, val, ncr_dev);
} else if (addr >= 0x1e00 && addr < 0x2000) {
if (ncr_dev->t128.host_pos < 512 && ncr->dma_mode == DMA_SEND) {
ncr_dev->t128.buffer[ncr_dev->t128.host_pos] = val;
ncr_dev->t128.host_pos++;
ncr_log("Write transfer, addr = %i, pos = %i, val = %02x\n", addr & 0x1ff, ncr_dev->t128.host_pos, val);
if (ncr_dev->t128.host_pos == 512) {
ncr_dev->t128.status &= ~0x04;
ncr_log("Transfer busy write, status = %02x\n", ncr_dev->t128.status);
timer_on_auto(&ncr_dev->timer, 0.02);
}
} else
ncr_log("Write PDMA addr = %i, val = %02x\n", addr & 0x1ff, val);
}
}
static void *
ncr_init(const device_t *info)
@@ -1218,6 +1469,22 @@ ncr_init(const device_t *info)
io_sethandler(ncr_dev->base, 16,
t130b_in,NULL,NULL, t130b_out,NULL,NULL, ncr_dev);
break;
case 3: /* Trantor T128 */
ncr_dev->rom_addr = device_get_config_hex20("bios_addr");
ncr_dev->irq = device_get_config_int("irq");
ncr_dev->t128.bios_enabled = device_get_config_int("boot");
ncr_dev->t128.int_lock = device_get_config_int("int_lock");
if (ncr_dev->t128.bios_enabled)
rom_init(&ncr_dev->bios_rom, T128_ROM,
ncr_dev->rom_addr, 0x4000, 0x3fff, 0, MEM_MAPPING_EXTERNAL);
mem_mapping_add(&ncr_dev->mapping, ncr_dev->rom_addr, 0x4000,
t128_read, NULL, NULL,
t128_write, NULL, NULL,
ncr_dev->bios_rom.rom, MEM_MAPPING_EXTERNAL, ncr_dev);
break;
}
sprintf(temp, "%s: BIOS=%05X", ncr_dev->name, ncr_dev->rom_addr);
@@ -1228,10 +1495,19 @@ ncr_init(const device_t *info)
ncr_log("%s\n", temp);
ncr_reset(ncr_dev, &ncr_dev->ncr);
ncr_dev->status_ctrl = STATUS_BUFFER_NOT_READY;
ncr_dev->buffer_host_pos = 128;
timer_add(&ncr_dev->timer, ncr_callback, ncr_dev, 0);
if (ncr_dev->type != 3) {
ncr_dev->status_ctrl = STATUS_BUFFER_NOT_READY;
ncr_dev->buffer_host_pos = 128;
} else {
ncr_dev->t128.status = 0x04;
ncr_dev->t128.host_pos = 512;
if (!ncr_dev->t128.bios_enabled)
ncr_dev->t128.status |= 0x80;
if (ncr_dev->t128.int_lock)
ncr_dev->t128.status |= 0x40;
}
timer_add(&ncr_dev->timer, ncr_callback, ncr_dev, 0);
return(ncr_dev);
}
@@ -1271,6 +1547,11 @@ t130b_available(void)
return(rom_present(T130B_ROM));
}
static int
t128_available(void)
{
return(rom_present(T128_ROM));
}
static const device_config_t ncr5380_mmio_config[] = {
{
@@ -1441,6 +1722,55 @@ static const device_config_t t130b_config[] = {
};
static const device_config_t t128_config[] = {
{
"bios_addr", "BIOS Address", CONFIG_HEX20, "", 0xD8000, "", { 0 },
{
{
"C800H", 0xc8000
},
{
"CC00H", 0xcc000
},
{
"D800H", 0xd8000
},
{
"DC00H", 0xdc000
},
{
""
}
},
},
{
"irq", "IRQ", CONFIG_SELECTION, "", 5, "", { 0 },
{
{
"IRQ 3", 3
},
{
"IRQ 5", 5
},
{
"IRQ 7", 7
},
{
""
}
},
},
{
"boot", "Enable Boot ROM", CONFIG_BINARY, "", 1
},
{
"int_lock", "Enable Handshake Interlock", CONFIG_BINARY, "", 0
},
{
"", "", -1
}
};
const device_t scsi_lcs6821n_device =
{
"Longshine LCS-6821N",
@@ -1473,3 +1803,14 @@ const device_t scsi_t130b_device =
NULL, NULL,
t130b_config
};
const device_t scsi_t128_device =
{
"Trantor T128",
DEVICE_ISA,
3,
ncr_init, ncr_close, NULL,
{ t128_available },
NULL, NULL,
t128_config
};

368
src/video/vid_paradise.c
View File

@@ -40,6 +40,8 @@ typedef struct paradise_t
rom_t bios_rom;
uint8_t pr0a, pr0b, pr1, pr5, bank_mask;
enum
{
PVGA1A = 0,
@@ -50,6 +52,23 @@ typedef struct paradise_t
uint32_t vram_mask;
uint32_t read_bank[4], write_bank[4];
int interlace;
struct {
uint8_t reg_block_ptr;
uint8_t reg_idx;
uint8_t disable_autoinc;
uint16_t int_status;
uint16_t blt_ctrl1, blt_ctrl2;
uint16_t srclow, srchigh;
uint16_t dstlow, dsthigh;
uint32_t srcaddr, dstaddr;
int invalid_block;
} accel;
} paradise_t;
static video_timings_t timing_paradise_pvga1a = {VIDEO_ISA, 6, 8, 16, 6, 8, 16};
@@ -57,79 +76,85 @@ static video_timings_t timing_paradise_wd90c = {VIDEO_ISA, 3, 3, 6, 5, 5, 1
void paradise_remap(paradise_t *paradise);
void paradise_out(uint16_t addr, uint8_t val, void *p)
{
paradise_t *paradise = (paradise_t *)p;
svga_t *svga = &paradise->svga;
uint8_t old;
uint8_t old, o;
if (paradise->vram_mask <= ((512 << 10) - 1))
paradise->bank_mask = 0x7f;
else
paradise->bank_mask = 0xff;
if (((addr & 0xfff0) == 0x3d0 || (addr & 0xfff0) == 0x3b0) && !(svga->miscout & 1))
addr ^= 0x60;
switch (addr)
{
case 0x3c5:
if (svga->seqaddr > 7)
if (svga->seqaddr > 7)
{
if (paradise->type < WD90C11 || svga->seqregs[6] != 0x48)
return;
return;
svga->seqregs[svga->seqaddr & 0x1f] = val;
if (svga->seqaddr == 0x11)
paradise_remap(paradise);
if (svga->seqaddr == 0x11) {
paradise_remap(paradise);
}
return;
}
break;
case 0x3cf:
if (svga->gdcaddr >= 0x9 && svga->gdcaddr < 0xf)
{
if ((svga->gdcreg[0xf] & 7) != 5)
return;
if (svga->gdcaddr >= 9 && svga->gdcaddr <= 0x0e) {
if ((paradise->pr5 & 7) != 5)
return;
}
if (svga->gdcaddr == 6)
{
if ((svga->gdcreg[6] & 0xc) != (val & 0xc))
{
switch (val&0xC)
{
case 0x0: /*128k at A0000*/
mem_mapping_set_addr(&svga->mapping, 0xa0000, 0x20000);
svga->banked_mask = 0xffff;
break;
case 0x4: /*64k at A0000*/
mem_mapping_set_addr(&svga->mapping, 0xa0000, 0x10000);
svga->banked_mask = 0xffff;
break;
case 0x8: /*32k at B0000*/
mem_mapping_set_addr(&svga->mapping, 0xb0000, 0x08000);
svga->banked_mask = 0x7fff;
break;
case 0xC: /*32k at B8000*/
mem_mapping_set_addr(&svga->mapping, 0xb8000, 0x08000);
svga->banked_mask = 0x7fff;
break;
}
}
svga->gdcreg[6] = val;
paradise_remap(paradise);
return;
}
if (svga->gdcaddr == 0x9 || svga->gdcaddr == 0xa || svga->gdcaddr == 0xb)
{
svga->gdcreg[svga->gdcaddr] = val;
paradise_remap(paradise);
return;
}
if (svga->gdcaddr == 0xd) {
svga->gdcreg[0xd] = val;
svga_recalctimings(svga);
return;
switch (svga->gdcaddr) {
case 6:
if (val & 8)
svga->banked_mask = 0x7fff;
else
svga->banked_mask = 0xffff;
if (svga->gdcreg[6] != val)
svga->gdcreg[6] = val;
paradise_remap(paradise);
break;
case 9:
paradise->pr0a = val & paradise->bank_mask;
paradise_remap(paradise);
break;
case 0x0a:
paradise->pr0b = val & paradise->bank_mask;
paradise_remap(paradise);
break;
case 0x0b:
paradise->pr1 = val;
paradise_remap(paradise);
break;
case 0x0d:
o = svga->gdcreg[0x0d];
svga->gdcreg[0x0d] = val;
if ((o ^ val) & 0x18)
svga_recalctimings(svga);
break;
case 0x0e:
o = svga->gdcreg[0x0e];
svga->gdcreg[0x0e] = val;
if ((o ^ val) & 0x01)
svga_recalctimings(svga);
break;
case 0x0c:
svga->gdcreg[0x0c] = val;
break;
case 0x0f:
paradise->pr5 = val;
break;
default:
svga->gdcreg[svga->gdcaddr] = val;
break;
}
if (svga->gdcaddr == 0xe) {
svga->gdcreg[0xe] = val;
svga_recalctimings(svga);
return;
}
break;
case 0x3D4:
@@ -148,7 +173,7 @@ void paradise_out(uint16_t addr, uint8_t val, void *p)
return;
old = svga->crtc[svga->crtcreg];
svga->crtc[svga->crtcreg] = val;
if (old != val)
{
if (svga->crtcreg < 0xe || svga->crtcreg > 0x10)
@@ -162,16 +187,10 @@ void paradise_out(uint16_t addr, uint8_t val, void *p)
}
}
}
switch (svga->crtcreg) {
case 0x2f:
if (paradise->type != PVGA1A)
svga->vram_display_mask = (val & 1) ? 0x3ffff : paradise->vram_mask;
break;
}
break;
}
svga_out(addr, val, svga);
svga_out(addr, val, svga);
}
uint8_t paradise_in(uint16_t addr, void *p)
@@ -184,40 +203,58 @@ uint8_t paradise_in(uint16_t addr, void *p)
switch (addr)
{
case 0x3c2:
return 0x10;
case 0x3c5:
if (svga->seqaddr > 7)
{
if (paradise->type < WD90C11 || svga->seqregs[6] != 0x48)
return 0xff;
if (svga->seqaddr > 0x12)
return 0xff;
return 0xff;
if (paradise->type < WD90C30) {
if (svga->seqaddr > 0x12)
return 0xff;
}
return svga->seqregs[svga->seqaddr & 0x1f];
}
break;
case 0x3cf:
if (svga->gdcaddr >= 0x9 && svga->gdcaddr < 0xf)
{
if (svga->gdcreg[0xf] & 0x10)
return 0xff;
switch (svga->gdcaddr)
{
case 0xf:
return (svga->gdcreg[0xf] & 0x17) | 0x80;
}
if (svga->gdcaddr >= 9 && svga->gdcaddr <= 0x0e) {
if ((paradise->pr5 & 7) != 5)
return 0xff;
}
switch (svga->gdcaddr) {
case 9:
return paradise->pr0a;
case 0x0a:
return paradise->pr0b;
case 0x0b:
if (paradise->vram_mask == (512 << 10) - 1) {
paradise->pr1 |= 0xc0;
paradise->pr1 &= ~0x40;
} else if (paradise->vram_mask == (1024 << 10) - 1) {
paradise->pr1 |= 0xc0;
if (svga->bpp >= 8 && !svga->lowres) /*Horrible tweak, but needed to get around black corruption in 1M mode*/
paradise->pr1 &= ~0x40;
}
return paradise->pr1;
case 6:
case 0x0c:
case 0x0d:
case 0x0e:
return svga->gdcreg[svga->gdcaddr];
case 0x0f:
return (paradise->pr5 & 0x17) | 0x80;
default:
return svga->gdcreg[svga->gdcaddr];
}
break;
case 0x3D4:
return svga->crtcreg;
case 0x3D5:
if ((paradise->type == PVGA1A) && (svga->crtcreg & 0x20))
return 0xff;
return 0xff;
if (svga->crtcreg > 0x29 && svga->crtcreg < 0x30 && (svga->crtc[0x29] & 0x88) != 0x80)
return 0xff;
return 0xff;
return svga->crtc[svga->crtcreg];
}
return svga_in(addr, svga);
@@ -227,46 +264,49 @@ void paradise_remap(paradise_t *paradise)
{
svga_t *svga = &paradise->svga;
uint8_t mask = (paradise->type == WD90C11) ? 0x7f : 0xff;
if (svga->seqregs[0x11] & 0x80)
{
paradise->read_bank[0] = paradise->read_bank[2] = (svga->gdcreg[0x9] & mask) << 12;
paradise->read_bank[1] = paradise->read_bank[3] = ((svga->gdcreg[0x9] & mask) << 12) + ((svga->gdcreg[6] & 0x08) ? 0 : 0x8000);
paradise->write_bank[0] = paradise->write_bank[2] = (svga->gdcreg[0xa] & mask) << 12;
paradise->write_bank[1] = paradise->write_bank[3] = ((svga->gdcreg[0xa] & mask) << 12) + ((svga->gdcreg[6] & 0x08) ? 0 : 0x8000);
}
else if (svga->gdcreg[0xb] & 0x08)
{
if (svga->gdcreg[0x6] & 0xc)
{
paradise->read_bank[0] = paradise->read_bank[2] = (svga->gdcreg[0xa] & mask) << 12;
paradise->write_bank[0] = paradise->write_bank[2] = (svga->gdcreg[0xa] & mask) << 12;
paradise->read_bank[1] = paradise->read_bank[3] = ((svga->gdcreg[0x9] & mask) << 12) + ((svga->gdcreg[6] & 0x08) ? 0 : 0x8000);
paradise->write_bank[1] = paradise->write_bank[3] = ((svga->gdcreg[0x9] & mask) << 12) + ((svga->gdcreg[6] & 0x08) ? 0 : 0x8000);
}
else
{
paradise->read_bank[0] = paradise->write_bank[0] = (svga->gdcreg[0xa] & mask) << 12;
paradise->read_bank[1] = paradise->write_bank[1] = ((svga->gdcreg[0xa] & mask) << 12) + ((svga->gdcreg[6] & 0x08) ? 0 : 0x8000);
paradise->read_bank[2] = paradise->write_bank[2] = (svga->gdcreg[0x9] & mask) << 12;
paradise->read_bank[3] = paradise->write_bank[3] = ((svga->gdcreg[0x9] & mask) << 12) + ((svga->gdcreg[6] & 0x08) ? 0 : 0x8000);
}
}
else
{
paradise->read_bank[0] = paradise->read_bank[2] = (svga->gdcreg[0x9] & mask) << 12;
paradise->read_bank[1] = paradise->read_bank[3] = ((svga->gdcreg[0x9] & mask) << 12) + ((svga->gdcreg[6] & 0x08) ? 0 : 0x8000);
paradise->write_bank[0] = paradise->write_bank[2] = (svga->gdcreg[0x9] & mask) << 12;
paradise->write_bank[1] = paradise->write_bank[3] = ((svga->gdcreg[0x9] & mask) << 12) + ((svga->gdcreg[6] & 0x08) ? 0 : 0x8000);
}
if (paradise->type == WD90C11) {
if (svga->seqregs[0x11] & 0x80) {
paradise->read_bank[0] = (paradise->pr0a) << 12;
paradise->read_bank[1] = paradise->read_bank[0] + ((svga->gdcreg[6] & 8) ? 0 : 0x8000);
paradise->read_bank[2] = paradise->read_bank[0];
paradise->read_bank[3] = paradise->read_bank[1];
paradise->write_bank[0] = (paradise->pr0b) << 12;
paradise->write_bank[1] = paradise->write_bank[0] + ((svga->gdcreg[6] & 8) ? 0 : 0x8000);
paradise->write_bank[2] = paradise->write_bank[0];
paradise->write_bank[3] = paradise->write_bank[1];
} else if (paradise->pr1 & 8) {
if (svga->gdcreg[6] & 0x0c) {
paradise->read_bank[0] = (paradise->pr0b) << 12;
paradise->read_bank[1] = ((paradise->pr0a) << 12) + ((svga->gdcreg[6] & 8) ? 0 : 0x8000);
paradise->read_bank[2] = paradise->read_bank[0];
paradise->read_bank[3] = paradise->read_bank[1];
paradise->write_bank[0] = (paradise->pr0b) << 12;
paradise->write_bank[1] = ((paradise->pr0a) << 12) + ((svga->gdcreg[6] & 8) ? 0 : 0x8000);
paradise->write_bank[2] = paradise->write_bank[0];
paradise->write_bank[3] = paradise->write_bank[1];
} else {
paradise->read_bank[0] = (paradise->pr0b) << 12;
paradise->read_bank[1] = paradise->read_bank[0] + ((svga->gdcreg[6] & 8) ? 0 : 0x8000);
paradise->read_bank[2] = (paradise->pr0a) << 12;
paradise->read_bank[3] = paradise->read_bank[2] + ((svga->gdcreg[6] & 8) ? 0 : 0x8000);
paradise->write_bank[0] = (paradise->pr0b) << 12;
paradise->write_bank[1] = paradise->write_bank[0] + ((svga->gdcreg[6] & 8) ? 0 : 0x8000);
paradise->write_bank[2] = (paradise->pr0a) << 12;
paradise->write_bank[3] = paradise->write_bank[2] + ((svga->gdcreg[6] & 8) ? 0 : 0x8000);
}
} else {
paradise->read_bank[0] = (paradise->pr0a) << 12;
paradise->write_bank[0] = (paradise->pr0a) << 12;
paradise->read_bank[1] = paradise->read_bank[0] + ((svga->gdcreg[6] & 8) ? 0 : 0x8000);
paradise->write_bank[1] = paradise->write_bank[0] + ((svga->gdcreg[6] & 8) ? 0 : 0x8000);
paradise->read_bank[2] = paradise->read_bank[0];
paradise->write_bank[2] = paradise->write_bank[0];
paradise->read_bank[3] = paradise->read_bank[0] + ((svga->gdcreg[6] & 8) ? 0 : 0x8000);
paradise->write_bank[3] = paradise->write_bank[0] + ((svga->gdcreg[6] & 8) ? 0 : 0x8000);
}
if (paradise->bank_mask == 0x7f) {
paradise->read_bank[1] &= 0x7ffff;
paradise->write_bank[1] &= 0x7ffff;
} else {
paradise->read_bank[1] &= 0xfffff;
paradise->write_bank[1] &= 0xfffff;
}
}
@@ -274,50 +314,73 @@ void paradise_recalctimings(svga_t *svga)
{
paradise_t *paradise = (paradise_t *) svga->p;
if (svga->gdcreg[0xd] & 0x08) svga->ma_latch |= 0x10000;
if (svga->gdcreg[0xd] & 0x10) svga->ma_latch |= 0x20000;
if (svga->gdcreg[0x0d] & 0x08) svga->ma_latch |= 0x10000;
if (svga->gdcreg[0x0d] & 0x10) svga->ma_latch |= 0x20000;
svga->lowres = !(svga->gdcreg[0x0e] & 0x01);
if (paradise->type == WD90C30) {
if (svga->crtc[0x3d] & 0x01) svga->vtotal |= 0x400;
if (svga->crtc[0x3d] & 0x02) svga->dispend |= 0x400;
if (svga->crtc[0x3d] & 0x04) svga->vsyncstart |= 0x400;
if (svga->crtc[0x3d] & 0x08) svga->vblankstart |= 0x400;
if (svga->crtc[0x3d] & 0x10) svga->split |= 0x400;
if (svga->crtc[0x3e] & 0x01) svga->vtotal |= 0x400;
if (svga->crtc[0x3e] & 0x02) svga->dispend |= 0x400;
if (svga->crtc[0x3e] & 0x04) svga->vsyncstart |= 0x400;
if (svga->crtc[0x3e] & 0x08) svga->vblankstart |= 0x400;
if (svga->crtc[0x3e] & 0x10) svga->split |= 0x400;
svga->interlace = (svga->crtc[0x2d] & 0x20);
}
svga->lowres = !(svga->gdcreg[0xe] & 0x01);
if (svga->bpp == 8 && !svga->lowres) {
svga->render = svga_render_8bpp_highres;
svga->interlace = !!(svga->crtc[0x2d] & 0x20);
if (!svga->interlace && svga->lowres && (svga->hdisp >= 1024) &&
((svga->gdcreg[5] & 0x60) == 0) && (svga->miscout >= 0x27) &&
(svga->miscout <= 0x2f) && ((svga->gdcreg[6] & 1) ||
(svga->attrregs[0x10] & 1))) { /*Horrible tweak to re-enable the interlace after returning to
a windowed DOS box in Win3.x*/
svga->interlace = 1;
}
}
if (svga->bpp >= 8 && !svga->lowres)
svga->render = svga_render_8bpp_highres;
}
static void paradise_write(uint32_t addr, uint8_t val, void *p)
{
paradise_t *paradise = (paradise_t *)p;
addr = (addr & 0x7fff) + paradise->write_bank[(addr >> 15) & 3];
svga_write_linear(addr, val, &paradise->svga);
svga_t *svga = &paradise->svga;
addr &= svga->banked_mask;
addr = (addr & 0x7fff) + paradise->write_bank[(addr >> 15) & 3];
svga_write_linear(addr, val, svga);
}
static void paradise_writew(uint32_t addr, uint16_t val, void *p)
{
paradise_t *paradise = (paradise_t *)p;
addr = (addr & 0x7fff) + paradise->write_bank[(addr >> 15) & 3];
svga_writew_linear(addr, val, &paradise->svga);
svga_t *svga = &paradise->svga;
addr &= svga->banked_mask;
addr = (addr & 0x7fff) + paradise->write_bank[(addr >> 15) & 3];
svga_writew_linear(addr, val, svga);
}
static uint8_t paradise_read(uint32_t addr, void *p)
{
paradise_t *paradise = (paradise_t *)p;
addr = (addr & 0x7fff) + paradise->read_bank[(addr >> 15) & 3];
return svga_read_linear(addr, &paradise->svga);
svga_t *svga = &paradise->svga;
addr &= svga->banked_mask;
addr = (addr & 0x7fff) + paradise->read_bank[(addr >> 15) & 3];
return svga_read_linear(addr, svga);
}
static uint16_t paradise_readw(uint32_t addr, void *p)
{
paradise_t *paradise = (paradise_t *)p;
addr = (addr & 0x7fff) + paradise->read_bank[(addr >> 15) & 3];
return svga_readw_linear(addr, &paradise->svga);
svga_t *svga = &paradise->svga;
addr &= svga->banked_mask;
addr = (addr & 0x7fff) + paradise->read_bank[(addr >> 15) & 3];
return svga_readw_linear(addr, svga);
}
void *paradise_init(const device_t *info, uint32_t memsize)
@@ -325,8 +388,6 @@ void *paradise_init(const device_t *info, uint32_t memsize)
paradise_t *paradise = malloc(sizeof(paradise_t));
svga_t *svga = &paradise->svga;
memset(paradise, 0, sizeof(paradise_t));
io_sethandler(0x03c0, 0x0020, paradise_in, NULL, NULL, paradise_out, NULL, NULL, paradise);
if (info->local == PVGA1A)
video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_paradise_pvga1a);
@@ -335,33 +396,38 @@ void *paradise_init(const device_t *info, uint32_t memsize)
switch(info->local) {
case PVGA1A:
svga_init(info, &paradise->svga, paradise, memsize, /*256kb*/
svga_init(info, svga, paradise, memsize, /*256kb*/
paradise_recalctimings,
paradise_in, paradise_out,
NULL,
NULL);
paradise->vram_mask = memsize - 1;
svga->decode_mask = memsize - 1;
break;
case WD90C11:
svga_init(info, &paradise->svga, paradise, 1 << 19, /*512kb*/
svga_init(info, svga, paradise, 1 << 19, /*512kb*/
paradise_recalctimings,
paradise_in, paradise_out,
NULL,
NULL);
paradise->vram_mask = (1 << 19) - 1;
svga->decode_mask = (1 << 19) - 1;
break;
case WD90C30:
svga_init(info, &paradise->svga, paradise, memsize,
svga_init(info, svga, paradise, memsize,
paradise_recalctimings,
paradise_in, paradise_out,
NULL,
NULL);
paradise->vram_mask = memsize - 1;
svga->decode_mask = memsize - 1;
break;
}
mem_mapping_set_handler(&svga->mapping, paradise_read, paradise_readw, NULL, paradise_write, paradise_writew, NULL);
mem_mapping_set_p(&svga->mapping, paradise);
mem_mapping_set_handler(&svga->mapping, paradise_read, paradise_readw, NULL, paradise_write, paradise_writew, NULL);
mem_mapping_set_p(&svga->mapping, paradise);
io_sethandler(0x03c0, 0x0020, paradise_in, NULL, NULL, paradise_out, NULL, NULL, paradise);
/* Common to all three types. */
svga->crtc[0x31] = 'W';
@@ -381,12 +447,12 @@ void *paradise_init(const device_t *info, uint32_t memsize)
break;
}
svga->bpp = 8;
svga->miscout = 1;
svga->bpp = 8;
svga->miscout = 1;
paradise->type = info->local;
paradise->type = info->local;
return paradise;
return paradise;
}
static void *paradise_pvga1a_ncr3302_init(const device_t *info)

120
src/video/vid_tgui9440.c
View File

@@ -131,7 +131,7 @@ typedef struct tgui_t
int pat_x, pat_y;
int use_src;
int pitch, bpp;
int src_pitch, dst_pitch, bpp;
uint32_t fill_pattern[8*8];
uint32_t mono_pattern[8*8];
uint32_t pattern_8[8*8];
@@ -1332,14 +1332,63 @@ tgui_accel_command(int count, uint32_t cpu_dat, tgui_t *tgui)
}
}
/*Other than mode stuff, this bit is undocumented*/
switch (tgui->accel.ger22 & 0xff) {
case 4:
tgui->accel.src_pitch = 1024;
tgui->accel.dst_pitch = 1024;
if (svga->hdisp == 800) {
if ((tgui->accel.ger22 >> 8) > 0) {
tgui->accel.src_pitch = 832;
tgui->accel.dst_pitch = 832;
}
}
break;
case 8:
tgui->accel.src_pitch = 2048;
tgui->accel.dst_pitch = 2048;
if (tgui->type >= TGUI_9660) {
tgui->accel.src_pitch = 1280;
tgui->accel.dst_pitch = 1280;
}
break;
case 9:
tgui->accel.src_pitch = 1024;
tgui->accel.dst_pitch = 1024;
if (tgui->type >= TGUI_9660) {
tgui->accel.src_pitch = svga->hdisp;
tgui->accel.dst_pitch = svga->hdisp;
if (svga->hdisp == 800) {
tgui->accel.src_pitch = 832;
tgui->accel.dst_pitch = 832;
}
}
break;
case 14:
tgui->accel.src_pitch = svga->hdisp;
tgui->accel.dst_pitch = svga->hdisp;
switch (tgui->svga.bpp) {
case 32:
if (svga->hdisp == 800) {
tgui->accel.src_pitch = 832;
tgui->accel.dst_pitch = 832;
}
break;
}
break;
}
switch (tgui->accel.command)
{
case TGUI_BITBLT:
if (count == -1) {
tgui->accel.src_old = tgui->accel.src_x + (tgui->accel.src_y * tgui->accel.pitch);
tgui->accel.src_old = tgui->accel.src_x + (tgui->accel.src_y * tgui->accel.src_pitch);
tgui->accel.src = tgui->accel.src_old;
tgui->accel.dst_old = tgui->accel.dst_x + (tgui->accel.dst_y * tgui->accel.pitch);
tgui->accel.dst_old = tgui->accel.dst_x + (tgui->accel.dst_y * tgui->accel.dst_pitch);
tgui->accel.dst = tgui->accel.dst_old;
tgui->accel.pat_x = tgui->accel.dst_x;
@@ -1424,8 +1473,8 @@ tgui_accel_command(int count, uint32_t cpu_dat, tgui_t *tgui)
tgui->accel.dy += ydir;
}
tgui->accel.src_old += (ydir * tgui->accel.pitch);
tgui->accel.dst_old += (ydir * tgui->accel.pitch);
tgui->accel.src_old += (ydir * tgui->accel.src_pitch);
tgui->accel.dst_old += (ydir * tgui->accel.dst_pitch);
tgui->accel.src = tgui->accel.src_old;
tgui->accel.dst = tgui->accel.dst_old;
@@ -1486,8 +1535,8 @@ tgui_accel_command(int count, uint32_t cpu_dat, tgui_t *tgui)
tgui->accel.pat_x = tgui->accel.dst_x;
tgui->accel.pat_y += ydir;
tgui->accel.src = tgui->accel.src_old = tgui->accel.src_old + (ydir * tgui->accel.pitch);
tgui->accel.dst = tgui->accel.dst_old = tgui->accel.dst_old + (ydir * tgui->accel.pitch);
tgui->accel.src = tgui->accel.src_old = tgui->accel.src_old + (ydir * tgui->accel.src_pitch);
tgui->accel.dst = tgui->accel.dst_old = tgui->accel.dst_old + (ydir * tgui->accel.dst_pitch);
tgui->accel.y++;
@@ -1533,8 +1582,8 @@ tgui_accel_command(int count, uint32_t cpu_dat, tgui_t *tgui)
tgui->accel.pat_x = tgui->accel.dst_x;
tgui->accel.pat_y += ydir;
tgui->accel.src = tgui->accel.src_old = tgui->accel.src_old + (ydir * tgui->accel.pitch);
tgui->accel.dst = tgui->accel.dst_old = tgui->accel.dst_old + (ydir * tgui->accel.pitch);
tgui->accel.src = tgui->accel.src_old = tgui->accel.src_old + (ydir * tgui->accel.src_pitch);
tgui->accel.dst = tgui->accel.dst_old = tgui->accel.dst_old + (ydir * tgui->accel.dst_pitch);
if (tgui->accel.y > tgui->accel.size_y)
return;
@@ -1547,10 +1596,10 @@ tgui_accel_command(int count, uint32_t cpu_dat, tgui_t *tgui)
case TGUI_SCANLINE:
{
if (count == -1) {
tgui->accel.src_old = tgui->accel.src_x + (tgui->accel.src_y * tgui->accel.pitch);
tgui->accel.src_old = tgui->accel.src_x + (tgui->accel.src_y * tgui->accel.src_pitch);
tgui->accel.src = tgui->accel.src_old;
tgui->accel.dst_old = tgui->accel.dst_x + (tgui->accel.dst_y * tgui->accel.pitch);
tgui->accel.dst_old = tgui->accel.dst_x + (tgui->accel.dst_y * tgui->accel.dst_pitch);
tgui->accel.dst = tgui->accel.dst_old;
tgui->accel.pat_x = tgui->accel.dst_x;
@@ -1584,8 +1633,8 @@ tgui_accel_command(int count, uint32_t cpu_dat, tgui_t *tgui)
tgui->accel.x = 0;
tgui->accel.pat_x = tgui->accel.dst_x;
tgui->accel.src = tgui->accel.src_old = tgui->accel.src_old + (ydir * tgui->accel.pitch);
tgui->accel.dst = tgui->accel.dst_old = tgui->accel.dst_old + (ydir * tgui->accel.pitch);
tgui->accel.src = tgui->accel.src_old = tgui->accel.src_old + (ydir * tgui->accel.src_pitch);
tgui->accel.dst = tgui->accel.dst_old = tgui->accel.dst_old + (ydir * tgui->accel.dst_pitch);
tgui->accel.pat_y += ydir;
return;
}
@@ -1642,13 +1691,13 @@ tgui_accel_command(int count, uint32_t cpu_dat, tgui_t *tgui)
}
while (count--) {
READ(tgui->accel.src_x + (tgui->accel.src_y * tgui->accel.pitch), src_dat);
READ(tgui->accel.src_x + (tgui->accel.src_y * tgui->accel.src_pitch), src_dat);
/*Note by TC1995: I suppose the x/y clipping max is always more than 0 in the TGUI 96xx, but the TGUI 9440 lacks clipping*/
if (steep) {
if ((tgui->type == TGUI_9440) || ((tgui->type >= TGUI_9660) && dx >= tgui->accel.left && dx <= tgui->accel.right &&
dy >= tgui->accel.top && dy <= tgui->accel.bottom)) {
READ(dx + (dy * tgui->accel.pitch), dst_dat);
READ(dx + (dy * tgui->accel.dst_pitch), dst_dat);
pat_dat = tgui->accel.fg_col;
@@ -1659,12 +1708,12 @@ tgui_accel_command(int count, uint32_t cpu_dat, tgui_t *tgui)
MIX();
WRITE(dx + (dy * tgui->accel.pitch), out);
WRITE(dx + (dy * tgui->accel.dst_pitch), out);
}
} else {
if ((tgui->type == TGUI_9440) || ((tgui->type >= TGUI_9660) && dy >= tgui->accel.left && dy <= tgui->accel.right &&
dx >= tgui->accel.top && dx <= tgui->accel.bottom)) {
READ(dy + (dx * tgui->accel.pitch), dst_dat);
READ(dy + (dx * tgui->accel.dst_pitch), dst_dat);
pat_dat = tgui->accel.fg_col;
@@ -1675,7 +1724,7 @@ tgui_accel_command(int count, uint32_t cpu_dat, tgui_t *tgui)
MIX();
WRITE(dy + (dx * tgui->accel.pitch), out);
WRITE(dy + (dx * tgui->accel.dst_pitch), out);
}
}
@@ -1707,29 +1756,15 @@ tgui_accel_out(uint16_t addr, uint8_t val, void *p)
tgui->accel.ger22 = (tgui->accel.ger22 & 0xff00) | val;
switch (val & 0xff) {
case 4:
tgui->accel.pitch = 1024;
tgui->accel.bpp = 0;
break;
case 8:
tgui->accel.pitch = 2048;
if (tgui->type >= TGUI_9660)
tgui->accel.pitch = 1280;
tgui->accel.bpp = 0;
break;
case 9:
tgui->accel.pitch = 1024;
if (tgui->type >= TGUI_9660) {
tgui->accel.pitch = tgui->svga.hdisp;
if (tgui->svga.hdisp == 800)
tgui->accel.pitch = 832;
}
tgui->accel.bpp = 1;
break;
case 14:
tgui->accel.pitch = tgui->svga.hdisp;
switch (tgui->svga.bpp) {
case 15:
case 16:
@@ -1741,14 +1776,11 @@ tgui_accel_out(uint16_t addr, uint8_t val, void *p)
break;
case 32:
if (tgui->svga.hdisp == 800) /*Weird oddball on Win95's side*/
tgui->accel.pitch = 832;
tgui->accel.bpp = 3;
break;
}
break;
}
break;
case 0x2123:
@@ -2171,29 +2203,15 @@ tgui_accel_write(uint32_t addr, uint8_t val, void *p)
tgui->accel.ger22 = (tgui->accel.ger22 & 0xff00) | val;
switch (val & 0xff) {
case 4:
tgui->accel.pitch = 1024;
tgui->accel.bpp = 0;
break;
case 8:
tgui->accel.pitch = 2048;
if (tgui->type >= TGUI_9660)
tgui->accel.pitch = 1280;
tgui->accel.bpp = 0;
break;
case 9:
tgui->accel.pitch = 1024;
if (tgui->type >= TGUI_9660) {
tgui->accel.pitch = tgui->svga.hdisp;
if (tgui->svga.hdisp == 800)
tgui->accel.pitch = 832;
}
tgui->accel.bpp = 1;
break;
case 14:
tgui->accel.pitch = tgui->svga.hdisp;
switch (tgui->svga.bpp) {
case 15:
case 16:
@@ -2205,8 +2223,6 @@ tgui_accel_write(uint32_t addr, uint8_t val, void *p)
break;
case 32:
if (tgui->svga.hdisp == 800) /*Weird oddball on Win95's side*/
tgui->accel.pitch = 832;
tgui->accel.bpp = 3;
break;
}