arm/dyncom: Migrate logging macros
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384849232b
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1e4eb7def8
@ -231,7 +231,7 @@ static unsigned int DPO(RotateRightByRegister)(ARMul_State* cpu, unsigned int sh
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}
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#define DEBUG_MSG \
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LOG_DEBUG(Core_ARM11, "inst is %x", inst); \
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NGLOG_DEBUG(Core_ARM11, "inst is {:x}", inst); \
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CITRA_IGNORE_EXIT(0)
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#define LnSWoUB(s) glue(LnSWoUB, s)
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@ -770,7 +770,7 @@ static ThumbDecodeStatus DecodeThumbInstruction(u32 inst, u32 addr, u32* arm_ins
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inst_index = table_length - 4;
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*ptr_inst_base = arm_instruction_trans[inst_index](tinstr, inst_index);
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} else {
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LOG_ERROR(Core_ARM11, "thumb decoder error");
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NGLOG_ERROR(Core_ARM11, "thumb decoder error");
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}
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break;
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case 28:
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@ -828,10 +828,10 @@ static unsigned int InterpreterTranslateInstruction(const ARMul_State* cpu, cons
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int idx;
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if (DecodeARMInstruction(inst, &idx) == ARMDecodeStatus::FAILURE) {
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LOG_ERROR(Core_ARM11, "Decode failure.\tPC: [0x%08" PRIX32 "]\tInstruction: %08" PRIX32,
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phys_addr, inst);
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LOG_ERROR(Core_ARM11, "cpsr=0x%" PRIX32 ", cpu->TFlag=%d, r15=0x%08" PRIX32, cpu->Cpsr,
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cpu->TFlag, cpu->Reg[15]);
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NGLOG_ERROR(Core_ARM11, "Decode failure.\tPC: [{:#010X}]\tInstruction: {:08X}", phys_addr,
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inst);
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NGLOG_ERROR(Core_ARM11, "cpsr={:#X}, cpu->TFlag={}, r15={:#010X}", cpu->Cpsr, cpu->TFlag,
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cpu->Reg[15]);
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CITRA_IGNORE_EXIT(-1);
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}
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inst_base = arm_instruction_trans[idx](inst, idx);
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@ -1802,7 +1802,7 @@ BIC_INST : {
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BKPT_INST : {
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if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
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bkpt_inst* const inst_cream = (bkpt_inst*)inst_base->component;
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LOG_DEBUG(Core_ARM11, "Breakpoint instruction hit. Immediate: 0x%08X", inst_cream->imm);
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NGLOG_DEBUG(Core_ARM11, "Breakpoint instruction hit. Immediate: {:#010X}", inst_cream->imm);
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}
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cpu->Reg[15] += cpu->GetInstructionSize();
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INC_PC(sizeof(bkpt_inst));
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@ -2017,7 +2017,7 @@ EOR_INST : {
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}
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LDC_INST : {
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// Instruction not implemented
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// LOG_CRITICAL(Core_ARM11, "unimplemented instruction");
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// NGLOG_CRITICAL(Core_ARM11, "unimplemented instruction");
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cpu->Reg[15] += cpu->GetInstructionSize();
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INC_PC(sizeof(ldc_inst));
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FETCH_INST;
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@ -2368,9 +2368,10 @@ MCRR_INST : {
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if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
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mcrr_inst* const inst_cream = (mcrr_inst*)inst_base->component;
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LOG_ERROR(Core_ARM11, "MCRR executed | Coprocessor: %u, CRm %u, opc1: %u, Rt: %u, Rt2: %u",
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inst_cream->cp_num, inst_cream->crm, inst_cream->opcode_1, inst_cream->rt,
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inst_cream->rt2);
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NGLOG_ERROR(Core_ARM11,
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"MCRR executed | Coprocessor: {}, CRm {}, opc1: {}, Rt: {}, Rt2: {}",
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inst_cream->cp_num, inst_cream->crm, inst_cream->opcode_1, inst_cream->rt,
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inst_cream->rt2);
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}
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cpu->Reg[15] += cpu->GetInstructionSize();
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@ -2451,9 +2452,10 @@ MRRC_INST : {
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if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
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mcrr_inst* const inst_cream = (mcrr_inst*)inst_base->component;
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LOG_ERROR(Core_ARM11, "MRRC executed | Coprocessor: %u, CRm %u, opc1: %u, Rt: %u, Rt2: %u",
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inst_cream->cp_num, inst_cream->crm, inst_cream->opcode_1, inst_cream->rt,
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inst_cream->rt2);
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NGLOG_ERROR(Core_ARM11,
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"MRRC executed | Coprocessor: {}, CRm {}, opc1: {}, Rt: {}, Rt2: {}",
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inst_cream->cp_num, inst_cream->crm, inst_cream->opcode_1, inst_cream->rt,
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inst_cream->rt2);
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}
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cpu->Reg[15] += cpu->GetInstructionSize();
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@ -3078,7 +3080,7 @@ SETEND_INST : {
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else
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cpu->Cpsr &= ~(1 << 9);
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LOG_WARNING(Core_ARM11, "SETEND %s executed", big_endian ? "BE" : "LE");
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NGLOG_WARNING(Core_ARM11, "SETEND {} executed", big_endian ? "BE" : "LE");
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cpu->Reg[15] += cpu->GetInstructionSize();
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INC_PC(sizeof(setend_inst));
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@ -3089,7 +3091,7 @@ SETEND_INST : {
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SEV_INST : {
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// Stubbed, as SEV is a hint instruction.
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if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
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LOG_TRACE(Core_ARM11, "SEV executed.");
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NGLOG_TRACE(Core_ARM11, "SEV executed.");
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}
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cpu->Reg[15] += cpu->GetInstructionSize();
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@ -3539,7 +3541,7 @@ SSAT16_INST : {
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STC_INST : {
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// Instruction not implemented
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// LOG_CRITICAL(Core_ARM11, "unimplemented instruction");
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// NGLOG_CRITICAL(Core_ARM11, "unimplemented instruction");
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cpu->Reg[15] += cpu->GetInstructionSize();
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INC_PC(sizeof(stc_inst));
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FETCH_INST;
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@ -4533,7 +4535,7 @@ UXTB16_INST : {
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WFE_INST : {
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// Stubbed, as WFE is a hint instruction.
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if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
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LOG_TRACE(Core_ARM11, "WFE executed.");
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NGLOG_TRACE(Core_ARM11, "WFE executed.");
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}
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cpu->Reg[15] += cpu->GetInstructionSize();
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@ -4545,7 +4547,7 @@ WFE_INST : {
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WFI_INST : {
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// Stubbed, as WFI is a hint instruction.
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if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
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LOG_TRACE(Core_ARM11, "WFI executed.");
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NGLOG_TRACE(Core_ARM11, "WFI executed.");
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}
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cpu->Reg[15] += cpu->GetInstructionSize();
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@ -4557,7 +4559,7 @@ WFI_INST : {
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YIELD_INST : {
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// Stubbed, as YIELD is a hint instruction.
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if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
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LOG_TRACE(Core_ARM11, "YIELD executed.");
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NGLOG_TRACE(Core_ARM11, "YIELD executed.");
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}
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cpu->Reg[15] += cpu->GetInstructionSize();
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@ -184,7 +184,7 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(cdp)(unsigned int inst, int index) {
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inst_cream->opcode_1 = BITS(inst, 20, 23);
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inst_cream->inst = inst;
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LOG_TRACE(Core_ARM11, "inst %x index %x", inst, index);
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NGLOG_TRACE(Core_ARM11, "inst {:x} index {:x}", inst, index);
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return inst_base;
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}
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static ARM_INST_PTR INTERPRETER_TRANSLATE(clrex)(unsigned int inst, int index) {
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