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Shader: Define a common interface for running vertex shader programs.

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This commit is contained in:
bunnei 2015-07-21 19:38:59 -04:00
parent 18527b9e21
commit 3f69c2039d
7 changed files with 289 additions and 186 deletions
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2
src/video_core/CMakeLists.txt
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@ -11,6 +11,7 @@ set(SRCS
pica.cpp
primitive_assembly.cpp
rasterizer.cpp
shader/shader.cpp
shader/shader_interpreter.cpp
utils.cpp
video_core.cpp
@ -35,6 +36,7 @@ set(HEADERS
primitive_assembly.h
rasterizer.h
renderer_base.h
shader/shader.h
shader/shader_interpreter.h
utils.h
video_core.h

5
src/video_core/command_processor.cpp
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@ -215,6 +215,9 @@ static inline void WritePicaReg(u32 id, u32 value, u32 mask) {
unsigned int vertex_cache_pos = 0;
vertex_cache_ids.fill(-1);
Shader::UnitState shader_unit;
Shader::Setup(shader_unit);
for (unsigned int index = 0; index < regs.num_vertices; ++index)
{
unsigned int vertex = is_indexed ? (index_u16 ? index_address_16[index] : index_address_8[index]) : index;
@ -307,7 +310,7 @@ static inline void WritePicaReg(u32 id, u32 value, u32 mask) {
&geometry_dumper, _1, _2, _3));
#endif
// Send to vertex shader
output = Shader::RunShader(input, attribute_config.GetNumTotalAttributes(), g_state.regs.vs, g_state.vs);
output = Shader::Run(shader_unit, input, attribute_config.GetNumTotalAttributes());
if (is_indexed) {
vertex_cache[vertex_cache_pos] = output;

6
src/video_core/pica.h
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@ -1083,6 +1083,7 @@ private:
// TODO: Perform proper arithmetic on this!
float value;
};
static_assert(sizeof(float24) == sizeof(float), "Shader JIT assumes float24 is implemented as a 32-bit float");
/// Struct used to describe current Pica state
struct State {
@ -1092,7 +1093,10 @@ struct State {
/// Vertex shader memory
struct ShaderSetup {
struct {
Math::Vec4<float24> f[96];
// The float uniforms are accessed by the shader JIT using SSE instructions, and are
// therefore required to be 16-byte aligned.
Math::Vec4<float24> MEMORY_ALIGNED16(f[96]);
std::array<bool, 16> b;
std::array<Math::Vec4<u8>, 4> i;
} uniforms;

105
src/video_core/shader/shader.cpp Normal file
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@ -0,0 +1,105 @@
// Copyright 2015 Citra Emulator Project
// Licensed under GPLv2 or any later version
// Refer to the license.txt file included.
#include "common/logging/log.h"
#include "common/profiler.h"
#include "video_core/debug_utils/debug_utils.h"
#include "video_core/pica.h"
#include "shader.h"
#include "shader_interpreter.h"
namespace Pica {
namespace Shader {
void Setup(UnitState& state) {
// TODO(bunnei): This will be used by the JIT in a subsequent commit
}
static Common::Profiling::TimingCategory shader_category("Vertex Shader");
OutputVertex Run(UnitState& state, const InputVertex& input, int num_attributes) {
auto& config = g_state.regs.vs;
auto& setup = g_state.vs;
Common::Profiling::ScopeTimer timer(shader_category);
state.program_counter = config.main_offset;
state.debug.max_offset = 0;
state.debug.max_opdesc_id = 0;
// Setup input register table
const auto& attribute_register_map = config.input_register_map;
if (num_attributes > 0) state.input_registers[attribute_register_map.attribute0_register] = input.attr[0];
if (num_attributes > 1) state.input_registers[attribute_register_map.attribute1_register] = input.attr[1];
if (num_attributes > 2) state.input_registers[attribute_register_map.attribute2_register] = input.attr[2];
if (num_attributes > 3) state.input_registers[attribute_register_map.attribute3_register] = input.attr[3];
if (num_attributes > 4) state.input_registers[attribute_register_map.attribute4_register] = input.attr[4];
if (num_attributes > 5) state.input_registers[attribute_register_map.attribute5_register] = input.attr[5];
if (num_attributes > 6) state.input_registers[attribute_register_map.attribute6_register] = input.attr[6];
if (num_attributes > 7) state.input_registers[attribute_register_map.attribute7_register] = input.attr[7];
if (num_attributes > 8) state.input_registers[attribute_register_map.attribute8_register] = input.attr[8];
if (num_attributes > 9) state.input_registers[attribute_register_map.attribute9_register] = input.attr[9];
if (num_attributes > 10) state.input_registers[attribute_register_map.attribute10_register] = input.attr[10];
if (num_attributes > 11) state.input_registers[attribute_register_map.attribute11_register] = input.attr[11];
if (num_attributes > 12) state.input_registers[attribute_register_map.attribute12_register] = input.attr[12];
if (num_attributes > 13) state.input_registers[attribute_register_map.attribute13_register] = input.attr[13];
if (num_attributes > 14) state.input_registers[attribute_register_map.attribute14_register] = input.attr[14];
if (num_attributes > 15) state.input_registers[attribute_register_map.attribute15_register] = input.attr[15];
state.conditional_code[0] = false;
state.conditional_code[1] = false;
RunInterpreter(state);
#if PICA_DUMP_SHADERS
DebugUtils::DumpShader(setup.program_code.data(), state.debug.max_offset, setup.swizzle_data.data(),
state.debug.max_opdesc_id, config.main_offset,
g_state.regs.vs_output_attributes); // TODO: Don't hardcode VS here
#endif
// Setup output data
OutputVertex ret;
// TODO(neobrain): Under some circumstances, up to 16 attributes may be output. We need to
// figure out what those circumstances are and enable the remaining outputs then.
for (int i = 0; i < 7; ++i) {
const auto& output_register_map = g_state.regs.vs_output_attributes[i]; // TODO: Don't hardcode VS here
u32 semantics[4] = {
output_register_map.map_x, output_register_map.map_y,
output_register_map.map_z, output_register_map.map_w
};
for (int comp = 0; comp < 4; ++comp) {
float24* out = ((float24*)&ret) + semantics[comp];
if (semantics[comp] != Regs::VSOutputAttributes::INVALID) {
*out = state.output_registers[i][comp];
} else {
// Zero output so that attributes which aren't output won't have denormals in them,
// which would slow us down later.
memset(out, 0, sizeof(*out));
}
}
}
// The hardware takes the absolute and saturates vertex colors like this, *before* doing interpolation
for (int i = 0; i < 4; ++i) {
ret.color[i] = float24::FromFloat32(
std::fmin(std::fabs(ret.color[i].ToFloat32()), 1.0f));
}
LOG_TRACE(Render_Software, "Output vertex: pos (%.2f, %.2f, %.2f, %.2f), col(%.2f, %.2f, %.2f, %.2f), tc0(%.2f, %.2f)",
ret.pos.x.ToFloat32(), ret.pos.y.ToFloat32(), ret.pos.z.ToFloat32(), ret.pos.w.ToFloat32(),
ret.color.x.ToFloat32(), ret.color.y.ToFloat32(), ret.color.z.ToFloat32(), ret.color.w.ToFloat32(),
ret.tc0.u().ToFloat32(), ret.tc0.v().ToFloat32());
return ret;
}
} // namespace Shader
} // namespace Pica

163
src/video_core/shader/shader.h Normal file
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@ -0,0 +1,163 @@
// Copyright 2015 Citra Emulator Project
// Licensed under GPLv2 or any later version
// Refer to the license.txt file included.
#pragma once
#include <boost/container/static_vector.hpp>
#include <nihstro/shader_binary.h>
#include "common/common_funcs.h"
#include "common/common_types.h"
#include "common/vector_math.h"
#include "video_core/pica.h"
using nihstro::RegisterType;
using nihstro::SourceRegister;
using nihstro::DestRegister;
namespace Pica {
namespace Shader {
struct InputVertex {
Math::Vec4<float24> attr[16];
};
struct OutputVertex {
OutputVertex() = default;
// VS output attributes
Math::Vec4<float24> pos;
Math::Vec4<float24> dummy; // quaternions (not implemented, yet)
Math::Vec4<float24> color;
Math::Vec2<float24> tc0;
Math::Vec2<float24> tc1;
float24 pad[6];
Math::Vec2<float24> tc2;
// Padding for optimal alignment
float24 pad2[4];
// Attributes used to store intermediate results
// position after perspective divide
Math::Vec3<float24> screenpos;
float24 pad3;
// Linear interpolation
// factor: 0=this, 1=vtx
void Lerp(float24 factor, const OutputVertex& vtx) {
pos = pos * factor + vtx.pos * (float24::FromFloat32(1) - factor);
// TODO: Should perform perspective correct interpolation here...
tc0 = tc0 * factor + vtx.tc0 * (float24::FromFloat32(1) - factor);
tc1 = tc1 * factor + vtx.tc1 * (float24::FromFloat32(1) - factor);
tc2 = tc2 * factor + vtx.tc2 * (float24::FromFloat32(1) - factor);
screenpos = screenpos * factor + vtx.screenpos * (float24::FromFloat32(1) - factor);
color = color * factor + vtx.color * (float24::FromFloat32(1) - factor);
}
// Linear interpolation
// factor: 0=v0, 1=v1
static OutputVertex Lerp(float24 factor, const OutputVertex& v0, const OutputVertex& v1) {
OutputVertex ret = v0;
ret.Lerp(factor, v1);
return ret;
}
};
static_assert(std::is_pod<OutputVertex>::value, "Structure is not POD");
static_assert(sizeof(OutputVertex) == 32 * sizeof(float), "OutputVertex has invalid size");
/**
* This structure contains the state information that needs to be unique for a shader unit. The 3DS
* has four shader units that process shaders in parallel. At the present, Citra only implements a
* single shader unit that processes all shaders serially. Putting the state information in a struct
* here will make it easier for us to parallelize the shader processing later.
*/
struct UnitState {
// The registers are accessed by the shader JIT using SSE instructions, and are therefore
// required to be 16-byte aligned.
Math::Vec4<float24> MEMORY_ALIGNED16(input_registers[16]);
Math::Vec4<float24> MEMORY_ALIGNED16(output_registers[16]);
Math::Vec4<float24> MEMORY_ALIGNED16(temporary_registers[16]);
u32 program_counter;
bool conditional_code[2];
// Two Address registers and one loop counter
// TODO: How many bits do these actually have?
s32 address_registers[3];
enum {
INVALID_ADDRESS = 0xFFFFFFFF
};
struct CallStackElement {
u32 final_address; // Address upon which we jump to return_address
u32 return_address; // Where to jump when leaving scope
u8 repeat_counter; // How often to repeat until this call stack element is removed
u8 loop_increment; // Which value to add to the loop counter after an iteration
// TODO: Should this be a signed value? Does it even matter?
u32 loop_address; // The address where we'll return to after each loop iteration
};
// TODO: Is there a maximal size for this?
boost::container::static_vector<CallStackElement, 16> call_stack;
struct {
u32 max_offset; // maximum program counter ever reached
u32 max_opdesc_id; // maximum swizzle pattern index ever used
} debug;
static int InputOffset(const SourceRegister& reg) {
switch (reg.GetRegisterType()) {
case RegisterType::Input:
return (int)offsetof(UnitState, input_registers) + reg.GetIndex()*sizeof(Math::Vec4<float24>);
case RegisterType::Temporary:
return (int)offsetof(UnitState, temporary_registers) + reg.GetIndex()*sizeof(Math::Vec4<float24>);
default:
UNREACHABLE();
return 0;
}
}
static int OutputOffset(const DestRegister& reg) {
switch (reg.GetRegisterType()) {
case RegisterType::Output:
return (int)offsetof(UnitState, output_registers) + reg.GetIndex()*sizeof(Math::Vec4<float24>);
case RegisterType::Temporary:
return (int)offsetof(UnitState, temporary_registers) + reg.GetIndex()*sizeof(Math::Vec4<float24>);
default:
UNREACHABLE();
return 0;
}
}
};
/**
* Performs any shader unit setup that only needs to happen once per shader (as opposed to once per
* vertex, which would happen within the `Run` function).
* @param state Shader unit state, must be setup per shader and per shader unit
*/
void Setup(UnitState& state);
/**
* Runs the currently setup shader
* @param state Shader unit state, must be setup per shader and per shader unit
* @param input Input vertex into the shader
* @param num_attributes The number of vertex shader attributes
* @return The output vertex, after having been processed by the vertex shader
*/
OutputVertex Run(UnitState& state, const InputVertex& input, int num_attributes);
} // namespace Shader
} // namespace Pica

135
src/video_core/shader/shader_interpreter.cpp
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@ -2,18 +2,14 @@
// Licensed under GPLv2 or any later version
// Refer to the license.txt file included.
#include <boost/container/static_vector.hpp>
#include <boost/range/algorithm.hpp>
#include <common/file_util.h>
#include <nihstro/shader_bytecode.h>
#include "common/profiler.h"
#include "video_core/pica.h"
#include "video_core/shader/shader_interpreter.h"
#include "video_core/debug_utils/debug_utils.h"
#include "shader.h"
#include "shader_interpreter.h"
using nihstro::OpCode;
using nihstro::Instruction;
@ -25,42 +21,7 @@ namespace Pica {
namespace Shader {
struct ShaderState {
u32 program_counter;
const float24* input_register_table[16];
Math::Vec4<float24> output_registers[16];
Math::Vec4<float24> temporary_registers[16];
bool conditional_code[2];
// Two Address registers and one loop counter
// TODO: How many bits do these actually have?
s32 address_registers[3];
enum {
INVALID_ADDRESS = 0xFFFFFFFF
};
struct CallStackElement {
u32 final_address; // Address upon which we jump to return_address
u32 return_address; // Where to jump when leaving scope
u8 repeat_counter; // How often to repeat until this call stack element is removed
u8 loop_increment; // Which value to add to the loop counter after an iteration
// TODO: Should this be a signed value? Does it even matter?
u32 loop_address; // The address where we'll return to after each loop iteration
};
// TODO: Is there a maximal size for this?
boost::container::static_vector<CallStackElement, 16> call_stack;
struct {
u32 max_offset; // maximum program counter ever reached
u32 max_opdesc_id; // maximum swizzle pattern index ever used
} debug;
};
static void ProcessShaderCode(ShaderState& state) {
void RunInterpreter(UnitState& state) {
const auto& uniforms = g_state.vs.uniforms;
const auto& swizzle_data = g_state.vs.swizzle_data;
const auto& program_code = g_state.vs.program_code;
@ -90,7 +51,7 @@ static void ProcessShaderCode(ShaderState& state) {
const Instruction instr = { program_code[state.program_counter] };
const SwizzlePattern swizzle = { swizzle_data[instr.common.operand_desc_id] };
static auto call = [](ShaderState& state, u32 offset, u32 num_instructions,
static auto call = [](UnitState& state, u32 offset, u32 num_instructions,
u32 return_offset, u8 repeat_count, u8 loop_increment) {
state.program_counter = offset - 1; // -1 to make sure when incrementing the PC we end up at the correct offset
ASSERT(state.call_stack.size() < state.call_stack.capacity());
@ -101,7 +62,7 @@ static void ProcessShaderCode(ShaderState& state) {
auto LookupSourceRegister = [&](const SourceRegister& source_reg) -> const float24* {
switch (source_reg.GetRegisterType()) {
case RegisterType::Input:
return state.input_register_table[source_reg.GetIndex()];
return &state.input_registers[source_reg.GetIndex()].x;
case RegisterType::Temporary:
return &state.temporary_registers[source_reg.GetIndex()].x;
@ -413,7 +374,7 @@ static void ProcessShaderCode(ShaderState& state) {
default:
{
static auto evaluate_condition = [](const ShaderState& state, bool refx, bool refy, Instruction::FlowControlType flow_control) {
static auto evaluate_condition = [](const UnitState& state, bool refx, bool refy, Instruction::FlowControlType flow_control) {
bool results[2] = { refx == state.conditional_code[0],
refy == state.conditional_code[1] };
@ -542,88 +503,6 @@ static void ProcessShaderCode(ShaderState& state) {
}
}
static Common::Profiling::TimingCategory shader_category("Vertex Shader");
OutputVertex RunShader(const InputVertex& input, int num_attributes, const Regs::ShaderConfig& config, const State::ShaderSetup& setup) {
Common::Profiling::ScopeTimer timer(shader_category);
ShaderState state;
state.program_counter = config.main_offset;
state.debug.max_offset = 0;
state.debug.max_opdesc_id = 0;
// Setup input register table
const auto& attribute_register_map = config.input_register_map;
float24 dummy_register;
boost::fill(state.input_register_table, &dummy_register);
if (num_attributes > 0) state.input_register_table[attribute_register_map.attribute0_register] = &input.attr[0].x;
if (num_attributes > 1) state.input_register_table[attribute_register_map.attribute1_register] = &input.attr[1].x;
if (num_attributes > 2) state.input_register_table[attribute_register_map.attribute2_register] = &input.attr[2].x;
if (num_attributes > 3) state.input_register_table[attribute_register_map.attribute3_register] = &input.attr[3].x;
if (num_attributes > 4) state.input_register_table[attribute_register_map.attribute4_register] = &input.attr[4].x;
if (num_attributes > 5) state.input_register_table[attribute_register_map.attribute5_register] = &input.attr[5].x;
if (num_attributes > 6) state.input_register_table[attribute_register_map.attribute6_register] = &input.attr[6].x;
if (num_attributes > 7) state.input_register_table[attribute_register_map.attribute7_register] = &input.attr[7].x;
if (num_attributes > 8) state.input_register_table[attribute_register_map.attribute8_register] = &input.attr[8].x;
if (num_attributes > 9) state.input_register_table[attribute_register_map.attribute9_register] = &input.attr[9].x;
if (num_attributes > 10) state.input_register_table[attribute_register_map.attribute10_register] = &input.attr[10].x;
if (num_attributes > 11) state.input_register_table[attribute_register_map.attribute11_register] = &input.attr[11].x;
if (num_attributes > 12) state.input_register_table[attribute_register_map.attribute12_register] = &input.attr[12].x;
if (num_attributes > 13) state.input_register_table[attribute_register_map.attribute13_register] = &input.attr[13].x;
if (num_attributes > 14) state.input_register_table[attribute_register_map.attribute14_register] = &input.attr[14].x;
if (num_attributes > 15) state.input_register_table[attribute_register_map.attribute15_register] = &input.attr[15].x;
state.conditional_code[0] = false;
state.conditional_code[1] = false;
ProcessShaderCode(state);
#if PICA_DUMP_SHADERS
DebugUtils::DumpShader(setup.program_code.data(), state.debug.max_offset, setup.swizzle_data.data(),
state.debug.max_opdesc_id, config.main_offset,
g_state.regs.vs_output_attributes); // TODO: Don't hardcode VS here
#endif
// Setup output data
OutputVertex ret;
// TODO(neobrain): Under some circumstances, up to 16 attributes may be output. We need to
// figure out what those circumstances are and enable the remaining outputs then.
for (int i = 0; i < 7; ++i) {
const auto& output_register_map = g_state.regs.vs_output_attributes[i]; // TODO: Don't hardcode VS here
u32 semantics[4] = {
output_register_map.map_x, output_register_map.map_y,
output_register_map.map_z, output_register_map.map_w
};
for (int comp = 0; comp < 4; ++comp) {
float24* out = ((float24*)&ret) + semantics[comp];
if (semantics[comp] != Regs::VSOutputAttributes::INVALID) {
*out = state.output_registers[i][comp];
} else {
// Zero output so that attributes which aren't output won't have denormals in them,
// which would slow us down later.
memset(out, 0, sizeof(*out));
}
}
}
// The hardware takes the absolute and saturates vertex colors like this, *before* doing interpolation
for (int i = 0; i < 4; ++i) {
ret.color[i] = float24::FromFloat32(
std::fmin(std::fabs(ret.color[i].ToFloat32()), 1.0f));
}
LOG_TRACE(Render_Software, "Output vertex: pos (%.2f, %.2f, %.2f, %.2f), col(%.2f, %.2f, %.2f, %.2f), tc0(%.2f, %.2f)",
ret.pos.x.ToFloat32(), ret.pos.y.ToFloat32(), ret.pos.z.ToFloat32(), ret.pos.w.ToFloat32(),
ret.color.x.ToFloat32(), ret.color.y.ToFloat32(), ret.color.z.ToFloat32(), ret.color.w.ToFloat32(),
ret.tc0.u().ToFloat32(), ret.tc0.v().ToFloat32());
return ret;
}
} // namespace
} // namespace

59
src/video_core/shader/shader_interpreter.h
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@ -4,68 +4,15 @@
#pragma once
#include <type_traits>
#include "common/vector_math.h"
#include "video_core/pica.h"
#include "shader.h"
namespace Pica {
namespace Shader {
struct InputVertex {
Math::Vec4<float24> attr[16];
};
struct OutputVertex {
OutputVertex() = default;
// VS output attributes
Math::Vec4<float24> pos;
Math::Vec4<float24> dummy; // quaternions (not implemented, yet)
Math::Vec4<float24> color;
Math::Vec2<float24> tc0;
Math::Vec2<float24> tc1;
float24 pad[6];
Math::Vec2<float24> tc2;
// Padding for optimal alignment
float24 pad2[4];
// Attributes used to store intermediate results
// position after perspective divide
Math::Vec3<float24> screenpos;
float24 pad3;
// Linear interpolation
// factor: 0=this, 1=vtx
void Lerp(float24 factor, const OutputVertex& vtx) {
pos = pos * factor + vtx.pos * (float24::FromFloat32(1) - factor);
// TODO: Should perform perspective correct interpolation here...
tc0 = tc0 * factor + vtx.tc0 * (float24::FromFloat32(1) - factor);
tc1 = tc1 * factor + vtx.tc1 * (float24::FromFloat32(1) - factor);
tc2 = tc2 * factor + vtx.tc2 * (float24::FromFloat32(1) - factor);
screenpos = screenpos * factor + vtx.screenpos * (float24::FromFloat32(1) - factor);
color = color * factor + vtx.color * (float24::FromFloat32(1) - factor);
}
// Linear interpolation
// factor: 0=v0, 1=v1
static OutputVertex Lerp(float24 factor, const OutputVertex& v0, const OutputVertex& v1) {
OutputVertex ret = v0;
ret.Lerp(factor, v1);
return ret;
}
};
static_assert(std::is_pod<OutputVertex>::value, "Structure is not POD");
static_assert(sizeof(OutputVertex) == 32 * sizeof(float), "OutputVertex has invalid size");
OutputVertex RunShader(const InputVertex& input, int num_attributes, const Regs::ShaderConfig& config, const State::ShaderSetup& setup);
void RunInterpreter(UnitState& state);
} // namespace