arm_dynarmic: Remove dependence on interpreter
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e04590a06d
commit
8b7b6e9f74
@ -103,8 +103,6 @@ void RegistersWidget::OnEmulationStopping() {
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vfp_system_registers->child(0)->setText(1, QString{});
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vfp_system_registers->child(1)->setText(1, QString{});
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vfp_system_registers->child(2)->setText(1, QString{});
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vfp_system_registers->child(3)->setText(1, QString{});
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setEnabled(false);
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}
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@ -188,16 +186,12 @@ void RegistersWidget::CreateVFPSystemRegisterChildren() {
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vfp_system_registers->addChild(fpscr);
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vfp_system_registers->addChild(fpexc);
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vfp_system_registers->addChild(new QTreeWidgetItem(QStringList(QStringLiteral("FPINST"))));
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vfp_system_registers->addChild(new QTreeWidgetItem(QStringList(QStringLiteral("FPINST2"))));
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}
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void RegistersWidget::UpdateVFPSystemRegisterValues() {
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// Todo: handle all cores
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const u32 fpscr_val = Core::GetCore(0).GetVFPSystemReg(VFP_FPSCR);
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const u32 fpexc_val = Core::GetCore(0).GetVFPSystemReg(VFP_FPEXC);
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const u32 fpinst_val = Core::GetCore(0).GetVFPSystemReg(VFP_FPINST);
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const u32 fpinst2_val = Core::GetCore(0).GetVFPSystemReg(VFP_FPINST2);
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QTreeWidgetItem* const fpscr = vfp_system_registers->child(0);
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fpscr->setText(1, QStringLiteral("0x%1").arg(fpscr_val, 8, 16, QLatin1Char('0')));
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@ -237,9 +231,4 @@ void RegistersWidget::UpdateVFPSystemRegisterValues() {
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fpexc->child(5)->setText(1, QString::number((fpexc_val >> 28) & 1));
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fpexc->child(6)->setText(1, QString::number((fpexc_val >> 30) & 1));
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fpexc->child(7)->setText(1, QString::number((fpexc_val >> 31) & 1));
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vfp_system_registers->child(2)->setText(
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1, QStringLiteral("0x%1").arg(fpinst_val, 8, 16, QLatin1Char('0')));
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vfp_system_registers->child(3)->setText(
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1, QStringLiteral("0x%1").arg(fpinst2_val, 8, 16, QLatin1Char('0')));
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}
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@ -9,7 +9,6 @@
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#include "common/microprofile.h"
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#include "core/arm/dynarmic/arm_dynarmic.h"
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#include "core/arm/dynarmic/arm_dynarmic_cp15.h"
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#include "core/arm/dyncom/arm_dyncom_interpreter.h"
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#include "core/core.h"
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#include "core/core_timing.h"
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#include "core/gdbstub/gdbstub.h"
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@ -102,24 +101,9 @@ public:
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}
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void InterpreterFallback(VAddr pc, std::size_t num_instructions) override {
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parent.interpreter_state->Reg = parent.jit->Regs();
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parent.interpreter_state->Cpsr = parent.jit->Cpsr();
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parent.interpreter_state->Reg[15] = pc;
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parent.interpreter_state->ExtReg = parent.jit->ExtRegs();
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parent.interpreter_state->VFP[VFP_FPSCR] = parent.jit->Fpscr();
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parent.interpreter_state->NumInstrsToExecute = num_instructions;
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InterpreterMainLoop(parent.interpreter_state.get());
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bool is_thumb = (parent.interpreter_state->Cpsr & (1 << 5)) != 0;
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parent.interpreter_state->Reg[15] &= (is_thumb ? 0xFFFFFFFE : 0xFFFFFFFC);
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parent.jit->Regs() = parent.interpreter_state->Reg;
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parent.jit->SetCpsr(parent.interpreter_state->Cpsr);
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parent.jit->ExtRegs() = parent.interpreter_state->ExtReg;
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parent.jit->SetFpscr(parent.interpreter_state->VFP[VFP_FPSCR]);
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parent.interpreter_state->ServeBreak();
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// Should never happen.
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UNREACHABLE_MSG("InterpeterFallback reached with pc = 0x{:08x}, code = 0x{:08x}, num = {}",
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pc, MemoryReadCode(pc), num_instructions);
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}
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void CallSVC(std::uint32_t swi) override {
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@ -135,11 +119,7 @@ public:
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if (GDBStub::IsConnected()) {
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parent.jit->HaltExecution();
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parent.SetPC(pc);
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Kernel::Thread* thread =
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parent.system.Kernel().GetCurrentThreadManager().GetCurrentThread();
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parent.SaveContext(thread->context);
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GDBStub::Break();
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GDBStub::SendTrap(thread, 5);
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parent.ServeBreak();
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return;
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}
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break;
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@ -169,12 +149,10 @@ public:
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Memory::MemorySystem& memory;
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};
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ARM_Dynarmic::ARM_Dynarmic(Core::System* system, Memory::MemorySystem& memory,
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PrivilegeMode initial_mode, u32 id,
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ARM_Dynarmic::ARM_Dynarmic(Core::System* system, Memory::MemorySystem& memory, u32 id,
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std::shared_ptr<Core::Timing::Timer> timer)
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: ARM_Interface(id, timer), system(*system), memory(memory),
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cb(std::make_unique<DynarmicUserCallbacks>(*this)) {
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interpreter_state = std::make_shared<ARMul_State>(system, memory, initial_mode);
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PageTableChanged();
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}
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@ -190,7 +168,11 @@ void ARM_Dynarmic::Run() {
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}
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void ARM_Dynarmic::Step() {
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cb->InterpreterFallback(jit->Regs()[15], 1);
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jit->Step();
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if (GDBStub::IsConnected()) {
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ServeBreak();
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}
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}
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void ARM_Dynarmic::SetPC(u32 pc) {
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@ -218,21 +200,25 @@ void ARM_Dynarmic::SetVFPReg(int index, u32 value) {
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}
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u32 ARM_Dynarmic::GetVFPSystemReg(VFPSystemRegister reg) const {
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if (reg == VFP_FPSCR) {
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switch (reg) {
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case VFP_FPSCR:
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return jit->Fpscr();
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case VFP_FPEXC:
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return fpexc;
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}
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// Dynarmic does not implement and/or expose other VFP registers, fallback to interpreter state
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return interpreter_state->VFP[reg];
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UNREACHABLE_MSG("Unknown VFP system register: {}", static_cast<size_t>(reg));
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}
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void ARM_Dynarmic::SetVFPSystemReg(VFPSystemRegister reg, u32 value) {
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if (reg == VFP_FPSCR) {
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switch (reg) {
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case VFP_FPSCR:
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jit->SetFpscr(value);
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return;
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case VFP_FPEXC:
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fpexc = value;
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return;
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}
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// Dynarmic does not implement and/or expose other VFP registers, fallback to interpreter state
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interpreter_state->VFP[reg] = value;
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UNREACHABLE_MSG("Unknown VFP system register: {}", static_cast<size_t>(reg));
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}
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u32 ARM_Dynarmic::GetCPSR() const {
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@ -244,11 +230,25 @@ void ARM_Dynarmic::SetCPSR(u32 cpsr) {
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}
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u32 ARM_Dynarmic::GetCP15Register(CP15Register reg) {
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return interpreter_state->CP15[reg];
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switch (reg) {
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case CP15_THREAD_UPRW:
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return cp15_state.cp15_thread_uprw;
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case CP15_THREAD_URO:
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return cp15_state.cp15_thread_uro;
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}
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UNREACHABLE_MSG("Unknown CP15 register: {}", static_cast<size_t>(reg));
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}
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void ARM_Dynarmic::SetCP15Register(CP15Register reg, u32 value) {
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interpreter_state->CP15[reg] = value;
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switch (reg) {
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case CP15_THREAD_UPRW:
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cp15_state.cp15_thread_uprw = value;
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return;
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case CP15_THREAD_URO:
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cp15_state.cp15_thread_uro = value;
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return;
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}
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UNREACHABLE_MSG("Unknown CP15 register: {}", static_cast<size_t>(reg));
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}
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std::unique_ptr<ARM_Interface::ThreadContext> ARM_Dynarmic::NewContext() const {
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@ -260,7 +260,7 @@ void ARM_Dynarmic::SaveContext(const std::unique_ptr<ThreadContext>& arg) {
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ASSERT(ctx);
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jit->SaveContext(ctx->ctx);
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ctx->fpexc = interpreter_state->VFP[VFP_FPEXC];
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ctx->fpexc = fpexc;
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}
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void ARM_Dynarmic::LoadContext(const std::unique_ptr<ThreadContext>& arg) {
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@ -268,7 +268,7 @@ void ARM_Dynarmic::LoadContext(const std::unique_ptr<ThreadContext>& arg) {
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ASSERT(ctx);
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jit->LoadContext(ctx->ctx);
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interpreter_state->VFP[VFP_FPEXC] = ctx->fpexc;
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fpexc = ctx->fpexc;
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}
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void ARM_Dynarmic::PrepareReschedule() {
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@ -278,11 +278,9 @@ void ARM_Dynarmic::PrepareReschedule() {
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}
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void ARM_Dynarmic::ClearInstructionCache() {
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// TODO: Clear interpreter cache when appropriate.
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for (const auto& j : jits) {
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j.second->ClearCache();
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}
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interpreter_state->instruction_cache.clear();
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}
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void ARM_Dynarmic::InvalidateCacheRange(u32 start_address, std::size_t length) {
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@ -303,11 +301,18 @@ void ARM_Dynarmic::PageTableChanged() {
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jits.emplace(current_page_table, std::move(new_jit));
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}
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void ARM_Dynarmic::ServeBreak() {
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Kernel::Thread* thread = system.Kernel().GetCurrentThreadManager().GetCurrentThread();
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SaveContext(thread->context);
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GDBStub::Break();
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GDBStub::SendTrap(thread, 5);
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}
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std::unique_ptr<Dynarmic::A32::Jit> ARM_Dynarmic::MakeJit() {
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Dynarmic::A32::UserConfig config;
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config.callbacks = cb.get();
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config.page_table = ¤t_page_table->pointers;
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config.coprocessors[15] = std::make_shared<DynarmicCP15>(interpreter_state);
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config.coprocessors[15] = std::make_shared<DynarmicCP15>(cp15_state);
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config.define_unpredictable_behaviour = true;
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return std::make_unique<Dynarmic::A32::Jit>(config);
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}
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@ -9,7 +9,7 @@
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#include <dynarmic/A32/a32.h>
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#include "common/common_types.h"
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#include "core/arm/arm_interface.h"
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#include "core/arm/skyeye_common/armstate.h"
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#include "core/arm/dynarmic/arm_dynarmic_cp15.h"
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namespace Memory {
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struct PageTable;
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@ -24,8 +24,8 @@ class DynarmicUserCallbacks;
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class ARM_Dynarmic final : public ARM_Interface {
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public:
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ARM_Dynarmic(Core::System* system, Memory::MemorySystem& memory, PrivilegeMode initial_mode,
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u32 id, std::shared_ptr<Core::Timing::Timer> timer);
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ARM_Dynarmic(Core::System* system, Memory::MemorySystem& memory, u32 id,
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std::shared_ptr<Core::Timing::Timer> timer);
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~ARM_Dynarmic() override;
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void Run() override;
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@ -55,14 +55,18 @@ public:
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void PageTableChanged() override;
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private:
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void ServeBreak();
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friend class DynarmicUserCallbacks;
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Core::System& system;
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Memory::MemorySystem& memory;
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std::unique_ptr<DynarmicUserCallbacks> cb;
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std::unique_ptr<Dynarmic::A32::Jit> MakeJit();
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u32 fpexc = 0;
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CP15State cp15_state;
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Dynarmic::A32::Jit* jit = nullptr;
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Memory::PageTable* current_page_table = nullptr;
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std::map<Memory::PageTable*, std::unique_ptr<Dynarmic::A32::Jit>> jits;
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std::shared_ptr<ARMul_State> interpreter_state;
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};
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@ -10,7 +10,7 @@ using Callback = Dynarmic::A32::Coprocessor::Callback;
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using CallbackOrAccessOneWord = Dynarmic::A32::Coprocessor::CallbackOrAccessOneWord;
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using CallbackOrAccessTwoWords = Dynarmic::A32::Coprocessor::CallbackOrAccessTwoWords;
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DynarmicCP15::DynarmicCP15(const std::shared_ptr<ARMul_State>& state) : interpreter_state(state) {}
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DynarmicCP15::DynarmicCP15(CP15State& state) : state(state) {}
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DynarmicCP15::~DynarmicCP15() = default;
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@ -26,24 +26,24 @@ CallbackOrAccessOneWord DynarmicCP15::CompileSendOneWord(bool two, unsigned opc1
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if (!two && CRn == CoprocReg::C7 && opc1 == 0 && CRm == CoprocReg::C5 && opc2 == 4) {
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// This is a dummy write, we ignore the value written here.
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return &interpreter_state->CP15[CP15_FLUSH_PREFETCH_BUFFER];
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return &state.cp15_flush_prefetch_buffer;
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}
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if (!two && CRn == CoprocReg::C7 && opc1 == 0 && CRm == CoprocReg::C10) {
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switch (opc2) {
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case 4:
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// This is a dummy write, we ignore the value written here.
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return &interpreter_state->CP15[CP15_DATA_SYNC_BARRIER];
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return &state.cp15_data_sync_barrier;
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case 5:
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// This is a dummy write, we ignore the value written here.
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return &interpreter_state->CP15[CP15_DATA_MEMORY_BARRIER];
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return &state.cp15_data_memory_barrier;
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default:
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return std::monostate{};
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}
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}
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if (!two && CRn == CoprocReg::C13 && opc1 == 0 && CRm == CoprocReg::C0 && opc2 == 2) {
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return &interpreter_state->CP15[CP15_THREAD_UPRW];
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return &state.cp15_thread_uprw;
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}
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return std::monostate{};
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@ -60,9 +60,9 @@ CallbackOrAccessOneWord DynarmicCP15::CompileGetOneWord(bool two, unsigned opc1,
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if (!two && CRn == CoprocReg::C13 && opc1 == 0 && CRm == CoprocReg::C0) {
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switch (opc2) {
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case 2:
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return &interpreter_state->CP15[CP15_THREAD_UPRW];
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return &state.cp15_thread_uprw;
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case 3:
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return &interpreter_state->CP15[CP15_THREAD_URO];
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return &state.cp15_thread_uro;
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default:
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return std::monostate{};
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}
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@ -8,13 +8,19 @@
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#include <dynarmic/A32/coprocessor.h>
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#include "common/common_types.h"
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struct ARMul_State;
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struct CP15State {
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u32 cp15_thread_uprw = 0;
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u32 cp15_thread_uro = 0;
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u32 cp15_flush_prefetch_buffer = 0; ///< dummy value
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u32 cp15_data_sync_barrier = 0; ///< dummy value
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u32 cp15_data_memory_barrier = 0; ///< dummy value
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};
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class DynarmicCP15 final : public Dynarmic::A32::Coprocessor {
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public:
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using CoprocReg = Dynarmic::A32::CoprocReg;
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explicit DynarmicCP15(const std::shared_ptr<ARMul_State>&);
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explicit DynarmicCP15(CP15State&);
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~DynarmicCP15() override;
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std::optional<Callback> CompileInternalOperation(bool two, unsigned opc1, CoprocReg CRd,
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@ -32,5 +38,5 @@ public:
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std::optional<u8> option) override;
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private:
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std::shared_ptr<ARMul_State> interpreter_state;
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CP15State& state;
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};
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@ -267,7 +267,7 @@ System::ResultStatus System::Init(Frontend::EmuWindow& emu_window, u32 system_mo
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#ifdef ARCHITECTURE_x86_64
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for (std::size_t i = 0; i < num_cores; ++i) {
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cpu_cores.push_back(
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std::make_shared<ARM_Dynarmic>(this, *memory, USER32MODE, i, timing->GetTimer(i)));
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std::make_shared<ARM_Dynarmic>(this, *memory, i, timing->GetTimer(i)));
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}
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#else
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for (std::size_t i = 0; i < num_cores; ++i) {
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