Implemented a PIIX register written to by the ZAPPA that is officially reserved on PIIX (but otherwise exists on PIIX3).

2021-09-17 02:54:19 +02:00
parent 89f1583a34
commit 626e8e58bb
1 changed files with 2 additions and 0 deletions
--- a/src/chipset/intel_piix.c
+++ b/src/chipset/intel_piix.c
@@ -528,6 +528,8 @@ piix_write(int func, int addr, uint8_t val, void *priv)
 	case 0xab:
 		if (dev->type == 3)
 			fregs[addr] &= (val & 0x01);
+		else if (dev->type < 3)
+			fregs[addr] = val;
 		break;
 	case 0xb0:
 		if (dev->type == 4)